MAX11410 Datasheet, PDF (26/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Reference Inputs
There are three selectable differential reference voltage
inputs. Select the reference input using bits REF_
SEL<2:0> in the CTRL register. Either VREFP, VREFN, or
both may be buffered, as determined by the REFBUFP_
EN and REFBUFN_EN bits. With the reference buffer
disabled, the input current is a few microamps (2.1µA/V,
typical). Enabling a reference buffer reduces the
reference input current to 65nA, typical. With the buffer
enabled, the common-mode voltage range for V_REFP
and V_REFN is between 100mV and V_AVDD - 100mV. With
the buffer disabled, the common-mode range is between
GND and V_AVDD.
Selectable buffers allow flexibility in using resistive voltage
references. For example, if a voltage reference is generated
by driving a current through a grounded reference
resistor, V_REFN may be unbuffered, allowing it to be connected
directly to GND, while V_REFP is buffered, helping reduce
the effect of input bias current on the reference voltage.
Low-Power Considerations
Several operating modes help to optimize power and
performance. As discussed in the Signal Path
Considerations section, applications that do not require
the gain or low input bias current available in PGA mode
can reduce supply current by 130µA by disabling the
PGA. For low-impedance sources, the input buffers
may be disabled for further power savings. Similarly, the
reference buffers may be disabled when the source
resistance is low. The modulator has a selectable “duty
cycle” mode for low power at lower sampling rates. The
IC may be placed into sleep mode between conversions
to reduce the average power-supply current.
Modulator Duty Cycle Mode
In addition to its normal operating mode, the modulator
can be operated in a 1/4 duty cycle mode to reduce power
consumption for a given data rate at the expense of noise.
The noise performance of a ΔΣ ADC generally improves
when increasing the OSR (lowering the output data rate)
because more samples of the internal modulator can be
averaged to yield one conversion result. In applications
where power consumption is critical, the improved noise
performance at low data rates may not be required. For
these applications, the internal duty cycling mode can
yield significant power savings by periodically entering
a low-power state between conversions. In principle,
the modulator runs in normal mode with a duty cycle
of 25%, performing one “normal” conversion and then
automatically entering a low-power state for three
consecutive conversion cycles. The noise performance
in duty-cycle mode is therefore comparable to the noise
performance in normal mode at four times the data
rate. The duty-cycle mode can be selected using Direct,
Buffered, or PGA signal paths. Neither the input buffers
nor PGA are duty cycled while in duty cycle mode.
Select duty-cycle mode using the CONV_TYPE bits in the
CONV_START register. To minimize current consumption
in duty-cycle mode, set the signal path for an appropriate
low-power mode (see the Signal Path Considerations
section).
Sleep Mode
Sleep mode (controlled by the PD register) powers down
all analog circuitry including the internal oscillator, resulting
in 0.5µA typical current consumption. Exit sleep mode
either by writing to the PD register or (when enabled) by
using a GPIO trigger.
Table 4. Analog Supply Current Comparison for Various Operating Modes
(Typical Values Shown)
FUNCTION
Normal Conversion, 60sps,
Buffers and PGA Off (Bypass Mode)
Duty-Cycle Conversion, 15sps,
Buffers and PGA Off (Bypass Mode)
Sleep Mode
Input Buffers
PGA
Reference Buffers Disabled
Reference Buffers Enabled (Each)
SUPPLY CURRENT
INPUT RANGE
390
AGND - 30mV to AV_DD + 30mV
280
0.5µA
35µA
130µA
—
17.5µA
AGND - 30mV to AV_DD + 30mV
N/A
AGND + 100mV to AV_DD - 100mV
AGND + 100mV to AV_DD - 100mV
AGND - 30mV to AV_DD + 30mV
AGND + 100mV to AV_DD - 100mV
INPUT CURRENT
1µA/V
1µA/V
—
65nA
1nA
2.1µA/V
61nA
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