 English |
|
|
|
|
|
|
|
| MAX11410 Datasheet, PDF (13/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power | |||
| |||
| ◁ |
MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Electrical Characteristics (continued)
(AVDD = +3.3V, VDDIO = +1.8V, VREFP - VREFN = AVDD, TA = TMIN to TMAX, unless otherwise noted., TA=+25°C for typical specifica-
tions, unless otherwise noted, Note 1 )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
POWER SPECIFICATIONS
Analog Supply
Interface Supply
AVDD
VDDIO
Sleep mode
2.7
3.6
V
1.7
3.6
V
0.5
3
Standby mode
115
150
Bypass mode, IDAC, VBIAS sources off,
AVDD = VREF = VIN = 3.6V, SINC4 filter,
continuous conversions at 60sps.
390
550
AVDD Currents
Buffered mode, IDAC, VBIAS sources off,
AVDD = VREF = VIN = 3.6V, SINC4 filter,
continuous conversions at 60sps.
PGA enabled, IDAC, VBIAS sources off,
AVDD = VREF = VIN = 3.6V, SINC4 filter,
continuous conversions at 60SPS.
TA = -40°C to 105°C
425
600
µA
700
PGA enabled, IDAC, VBIAS sources off,
AVDD = VREF = VIN = 3.6V, SINC4 filter,
continuous conversions at 60sps.
TA = -40°C to 125°C.
520
750
VDDIO Operating
Current
All modes of operation
0.3
2
µA
VDDREG Current
Bypass mode, IDAC, VBIAS sources off,
AVDD = VREF = VIN = 3.6V, SINC4 filter,
continuous conversions at 15sps.
48
µA
280
380
AVDD Duty Cycle
Power Mode
Buffered mode, IDAC, VBIAS sources off,
AVDD = VREF = VIN = 3.6V, SINC4 filter,
continuous conversions at 15sps.
300
400
µA
PGA enabled, IDAC, VBIAS sources off,
AVDD = VREF = VIN = 3.6V, SINC4 filter,
continuous conversions at 15sps.
400
580
SPI TIMING SPECIFICATIONS
SCLK Frequency
SCLK Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
fSCLK
tSCLK
tCH
tCL
0
8
MHz
125
ns
50
ns
50
ns
www.maximintegrated.com
Maxim Integrated ââ 13
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese