MAX11410 Datasheet, PDF (82/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Example 3: The following sequence is written
CONV_START, 0x00 (DATA_RDY is set) CONV_START, 0x20
CONV_START, 0x40
CONV_START, 0x60
DATA_RDY[0], DATA_RDY[2], DATA_RDY[4], and DATA_RDY[6] are set internally, thereby setting the DATA_RDY status
bit after the first conversion is complete. The ATA0, DATA2, DATA4, and DATA6 registers are then read. After the last
DATA register is read, all corresponding internal registers are cleared, and the DATA_RDY status bit is cleared.
The WAIT_DONE bit indicates that the WAIT operation has completed. This status is cleared by a read of the status
register or a write to the WAIT_START register
The CAL_RDY bit indicates that a new calibration result is available in the SYS_CAL or SELF_CAL registers. CAL_RDY
is cleared by a read of the status register or a write to the CAL_START register.
The SEQ_RDY bit indicates that an initiated sequence has completed at least one iteration. SEQ_RDY is cleared by a
read of the status register, a write to the SEQ_START register (including within a sequence), or a sequence wraparound
from µC52->µC0.
The CONV_RDY bit indicates that a new conversion result is available in the DATA registers. CONV_RDY is cleared by a
read of the status register, a write to the CONV_START register (including within a sequence), or prior to the availability
of a new conversion result in continuous or duty cycle mode.
BIT
Field
Reset
Access Type
23
TOR_7
Read Only
22
TOR_6
Read Only
21
TOR_5
Read Only
20
TOR_4
Read Only
19
TOR_3
Read Only
18
TOR_2
Read Only
17
TOR_1
Read Only
16
TOR_0
Read Only
Bit
Field
Reset
Access Type
15
TUR_7
Read Only
14
TUR_6
Read Only
13
TUR_5
Read Only
12
TUR_4
Read Only
11
TUR_3
Read Only
10
TUR_2
Read Only
9
TUR_1
Read Only
8
TUR_0
Read Only
Bit
7
Field
SYSGOR
Reset
Access Type Write, Read
BITFIELD
BITS
TOR_7
23
TOR_6
22
6
5
4
–
–
–
–
–
–
–
–
–
DESCRIPTION
3
WAIT_
DONE
2
1
0
CAL_RDY SEQ_RDY CONV_RDY
Write, Read Write, Read Write, Read Write, Read
DECODE
0: Normal operation
1: Threshold overrange/digital overrange condition on
channel 7. Clears when the STATUS register is read.
0: Normal operation
1: Threshold overrange/digital overrange condition on
channel 6. Clears when the STATUS register is read.
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