MAX11410 Datasheet, PDF (21/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Detailed Description
This low-power, multi-channel, 24-bit delta-sigma ADC
has features and specifications that are optimized for
precision measurement of sensors and other analog
signal sources.
The input section includes a low-noise programmable
gain amplifier (PGA) with very high input impedance and
available gains from 1x to 128x to optimize the overall
dynamic range. Low-power input buffers may be enabled
to provide isolation of the signal source from the modulator's
switched-capacitor sampling network when the PGA is
not in use, reducing the supply current requirements
compared to the PGA.
Several integrated features simplify precision sensor
applications. The programmable matched current sources
provide excitation for resistive sensors; sixteen different
current levels are available, allowing sensor full-scale
range to be tuned for optimum signal-to-noise ratio. An
additional current sink and current source supply small
current levels to aid in detecting broken sensor wires. The
5-channel differential/10-channel single-ended multiplexer
provides the flexibility needed for complex multi-sensor
measurements. GPIOs reduce isolation components and
ease control of switches or other circuitry.
The ADC can operate in continuous conversion mode at
data rates up to 1920sps, and in single-cycle conversion
mode at rates up to 480sps. When used in single-cycle
mode, the digital filter settles within a single conversion
cycle. The available FIR digital filter allows single-cycle
settling in 16ms while providing more than 90dB
simultaneous rejection of 50Hz and 60Hz line noise.
The integrated on-chip oscillator requires no external
components. If needed, an external clock source may be
used instead. Control registers and conversion data are
accessed through the SPI-compatible serial interface.
Analog Inputs
The ten analog inputs (AIN0–AIN9) are configurable for
differential/single-ended operation. For each conversion,
the input multiplexer can be configured such that any of
the ten analog inputs or AVDD can be used as the positive
input. Additionally, any of the ten analog inputs or AGND
can be used as the negative input for the differential
measurement. The multiplexer outputs may either drive
the ADC inputs directly or drive low-power buffers. They
then drive the ADC or the PGA inputs.
AIN0 and AIN1 are internally connected to the reference
multiplexer. When used as reference inputs, they serve as
REF0P and REF0N.
Each of the two current sources (IDAC0 and IDAC1)
can be routed to any of the ten analog inputs. The bias
voltage source (V_BIAS) can be routed to any of analog
inputs AIN0–AIN7.
Signal Path Considerations
Three signal-path options are available to trade power-
supply current against input impedance, gain, and input
voltage range by enabling the PGA or the input buffers,
or bypassing both and driving the modulator directly. The
PGA control register selects among these options, which
are summarized below.
Bypass (Direct Signal Path) Mode
In bypass mode, the multiplexer outputs are directly
connected to the ADC modulator inputs. In this mode,
the input buffer and the PGA are disabled for minimum
power-supply current. This mode allows input voltages
from V_AGND - 30mV to V_AVDD + 30mV, and adds
no amplifier noise to the signal. Input bias current is
typically 1µA/V, which is appropriate when driving with a
low source resistance.
For smaller signal amplitudes, “digital gains” of 2 and 4
are available when using the direct signal path. See the
Digital Gain section for more information.
Buffered Mode
In buffered mode, the multiplexer outputs drive the inputs
to the low-power signal buffers, which then drive the ADC
modulator inputs. Selecting buffered mode disables the
PGA. Input voltages from V_AGND + 100mV to V_AVDD -
100mV are accepted in this mode, and no amplifier noise
is added to the signal. The input bias current, typically
61nA, is significantly less than that in the direct mode, so
higher source resistances may be accommodated without
causing appreciable errors. Enabling the input buffers
increases the power supply current by 35µA (typical)
compared to the bypassed (direct signal path) mode.
As with the bypassed mode, digital gains of 2 and 4 are
available when using the buffered mode. See the Digital
Gain section for more information.
PGA Mode
The programmable gain amplifier (PGA) provides gains of
1, 2, 4, 8, 16, 32, 64, or 128. Selecting PGA mode enables
the PGA, connects the PGA inputs to the multiplexer
outputs, connects the PGA outputs to the ADC modulator
inputs, and disables the low-power input buffers. The PGA
accepts input voltages from V_AGND + 100mV to V_AVDD -
100mV for gains up to 16, and V_AGND + 200mV to V_AVDD
- 200mV for gains from 32 to 128. When enabled, the
PGA supply current is typically 130µA.
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