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MAX11410 Datasheet, PDF (12/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power
MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Electrical Characteristics (continued)
(AVDD = +3.3V, VDDIO = +1.8V, VREFP - VREFN = AVDD, TA = TMIN to TMAX, unless otherwise noted., TA=+25°C for typical specifica-
tions, unless otherwise noted, Note 1 )
PARAMETER
LDO
LDO Output
Capacitance
LDO Output Voltage
System Timing
Power-On Wake-Up
Time
Sleep Wake-Up Time
PGA Power-Up Time
PGA Settling Time
Input Multiplexer
Power-Up Time
Input Multiplexer
Channel-to-Channel
Settling Time
VBIAS Power-Up Time
VBIAS Settling Time
Matched Current Source
Startup Time
Matched Current Source
Settling Time
SYMBOL
CONDITIONS
MIN
100
1.62
From AVDD > VPOR
CFILTER = 0
CFILTER = 20nF
CFILTER = 100nF
After changing gain settings to Gain = 1.
CFILTER = 0.
After changing gain settings to Gain = 1.
CFILTER = 100nF.
After changing gain settings to Gain = 128.
CFILTER = 0.
Settled to 21 bits with 10pF load
Settled to 21 bits with 2K external source
resistor
Active generator; settled within 1% of final
value; CLOAD = 1µF
125K passive generator; settled within 1%
of final value; CLOAD = 1µF
20K passive generator; settled within 1% of
final value; CLOAD = 1µF
Active generator; settled within 1% of final
value; CLOAD = 1µF
125K passive generator; settled within 1%
of final value; CLOAD = 1µF
20K passive generator; settled within 1% of
final value; CLOAD = 1µF
TYP
1.8
240
1.25
0.25
2
10
0.25
10
2
2
2
10
575
90
10
605
100
110
12.5
MAX UNITS
nF
1.98
V
µs
ms
ms
ms
µs
µs
ms
ms
µs
µs
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