MAX11410 Datasheet, PDF (31/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Table 7d. Example of System Gain Calibration
STEP
1
DESCRIPTION
REGISTER
Apply “System Full-
Scale”
N/A
COMMENTS
Apply an input voltage that should result in a full-scale conversion result to the
appropriate analog input(s).
2
Select Filter and
Rate
FILTER (0x08)
For best results, select a rate no faster than the rate that will be used for
conversions. A slower rate will result in more accurate calibration.
3
Select Reference
Input
CTRL (0x09)
For best results, select a reference voltage equal to or near value that will be used
for conversions.
4
Set Input Multi-
plexer
MUX_CNTRL0
(0x0B)
Select inputs to which “system full-scale” is applied.
5
Select Gain and
Signal Path
PGA (0x0E)
For best results, select the signal path that will be used for conversions. Select the
gain that, when combined with the applied input voltage, yields a full-scale
conversion result .
6
Select Clock
Source and Format
CTRL (0x11)
For best results, select the clock source (internal or external) that will be used for
conversions. If external clock is selected, ensure that the external clock is
operating before beginning calibration. Format selection doesn’t affect results.
Select System
7 Offset and Start
Calibration
CAL_START
Write XXXXX101 to store in SYS_GAIN_A register or XXXXX111 to store in
SYS_GAIN_B register.
GPIOs
Two general-purpose digital IOs increase the ADC's flexibility.
When used as an output, a GPIO can be used as a
microcontroller interrupt, a control signal for a multiplexer
or multichannel switch, or a modulator clock output. GPIO
pins configured as outputs operate on the AVDD rail. Care
should be taken when using the GPIO pins in input mode
to avoid bringing the signal above V_AVDD + 0.3V.
When configured as an input, a GPIO can be used as an
external clock input, an ADC start control, or a sequence
start control. When using GPIO0 as external clock input
(EXTCLK = 1), apply a 2.4576MHz clock signal to the
pin. Other frequencies can be used, but the data rate and
digital filter notch frequencies scale accordingly. GPIO
pins configured as inputs accept inputs at V_DDIO levels
(not to exceed AV_DD).
The GPIO ports are configurable with the GP0_CTRL
and GP1_CTRL registers. The registers select whether
a GPIO will be used as an input or as an output, and if
used as an output, the output configuration (CMOS/open-
drain).
Low-Side Power Switch
The GPIO pins can be configured to function as a low-
side power switch with less than 35Ω on-resistance
(25mA switch current) to reduce system power consumption
in bridge sensor applications by powering down a bridge
circuit between conversions.
Select automatic low-side switch operation by setting the
GP_OSEL and GP_DIR register bits:
GP0_CTRL = 1000_0101 (switch normally open, closed
during ADC conversions)
"Manually" control the low-side power switch by configuring
a GPIO as an open-drain output, and switch between
state Logic 0 and Logic 1:
GP0_CTRL = 1000_0100 (Logic 0, switch closed)
GP0_CTRL = 1000_0100 (Logic 1, switch open)
GP0_CTRL = 1000_0100 (Logic 0, switch closed)
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