ISL78229 Datasheet, PDF (7/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

Block Diagram
VIN
HIC/LATCH
PGOOD
NTC
EN
PVCC
VCC
SS
ATRK/DTRK
TRACK
FB
COMP
IMON
EN
1.2V
÷ 48 ^VIN/48
1.21V
VIN_OV
5.2V
LDO
POR
PLL
EN
1.2*VREF_DAC
3 bits [2:0] ^(Default)
D3h
VREF_
VOUTOV
OTP DEFAULT
D2h
VFB
SELECTION
3 bits [2:0]
HICCUP
/LATCH-OFF
D4h
VREF_
VOUTUV
0.8*VREF_DAC
EN_HICCP
(Default)
EN_LATCHOFF
INITIALIZATION
DELAY
HICCUP
RETRY
DELAY
LATCH-OFF
LOGIC
5µA
EN_SS
SOFT-START
DELAY AND
LOGIC
3.47V
SS
SS_DONE
VOUT_OV
VOUT_UV
20µA
VNTC
VIN/48 ^M
VFB
U
X
VIMON
10-bit
ADC
EN
Rising
Delay
VIN_OV
VOUT_OV
VOUT_UV
OC_AVG
OC2_PEAK_PH1
OC2_PEAK_PH2
OT_NTC_FAULT
OT_NTC_WARN
PLLCOMP_SHORT
PLL_LOCK
LOGIC
AND REGISTERS
FAULT
I²C/PMBus
INTERFACE
CLOCK
VCO
PLL
SLOPE
COMPENSATION
112µA
ATRAK/
DTRK
1k
0.3V
VREF_TRK
VREF_2.5V
SS
M
LP
VREF_TRK
U
X
Filter VREF_DAC
(1.6V Default)
VFB
8 bits [7:0]
21h
8-bit
DAC
Gm1
PWM
Comparator
VRAMP
OC2_PH1
OC1_PH1
OC_NEG_PH1
ZCD_PH1
ISEN1
ISEN1
105µA _ISEN1
80µA
ISEN1
-48µA _ISEN1
2µA
CSA
IBIAS
112µA
1.6V
3 bits [2:0]
(DEFAULT)
DCC
D5h
VREF_CC
Gm2
1.1V
CMP_PD
PHASE_DROP
3 bits [2:0]
D6h
VIMON
IOUT
CMP_OCAVG
VREF_
OCAVG
2V
(DEFAULT)
OC_AVG
FAULT
R2
R1 Q
CLOCK _S
PWM CONTROL
PROGRAMMABLE
ADAPTIVE DEAD
TIME
PVCC
DUPLICATE FOR EACH PHASE
PGND
÷8
ISEN1
(PH1)

17µA

÷8
ISEN2
(PH2)
DROP_PHASE2
PHASE DROP
CONTROL
EN_DE
EN_PHASE_DROP
DE MODE
AND PHASE DROP
MODE
SELECTION
N.C.
SGND
PAD
FIGURE 3. BLOCK DIAGRAM
ADDR1
ADDR2
SDA
SCL
SALERT
FSYNC
PLLCOMP
CLKOUT
SLOPE
ISEN1P
ISEN1N
BOOT1
UG1
PH1
LG1
PGND
RDT
RBLANK
DE/PHDRP