ISL78229 Datasheet, PDF (36/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
If the FB pin voltage is lower than 80% (default) of the voltage
regulation reference VREF_DAC, the VOUT_UV comparator is
triggered to indicate VOUT_UV fault and the PGOOD pin will be
pulled low. Also, corresponding bit (VOUT_UV, Bit [6]) in the
FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h)
and SALERT Signal” on page 34 and Table 3 on page 41) is set to
1 and the SALERT pin is pulled low.
When the output voltage rises back to be above the VOUT_UV
threshold 80% VREF_DAC plus 4% hysteresis, PGOOD will be
released to be pulled HIGH after a 0.5ms delay. However, as
described in the “Fault Flag Register FAULT_STATUS (D0h) and
SALERT Signal” on page 34, the bit = 1 status in the
FAULT_STATUS register will not be automatically cleared/reset to
0 by the device itself and the SALERT pin is kept low. The bits in
the FAULT_STATUS register can only be cleared to 0 by a Write
command, or CLEAR_FAULTS command via PMBus™, or EN/POR
recycling. When all the bits in the FAULT_STATUS register are 0,
the SALERT pin is released to be pulled HIGH.
The VOUT_UV fault protection response is disabled (ignored) by
default as the VOUT_UV bit (Bit [6]) is set 1 as default in the
FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK
(D1h)” on page 35 and Table 3 on page 41), which means the
ISL78229 keeps the PWM switching and normal operation when
VOUT_UV fault occurs. VOUT_UV fault protection can be enabled
by setting set this VOUT_UV bit (Bit [6]) to 0 in the “Fault Mask
Register FAULT_MASK (D1h)” on page 35. If enabled, the fault
response can be programmed to be either Hiccup or Latch-off as
described in “Fault Response Register SET_FAULT_RESPONSE
(D2h)” on page 35 and Table 3 on page 41.
The VOUT_UV threshold values can be set to 8 options based on
percentage of the reference VREF_DAC via PMBus™ command
“VOUT_UV_FAULT_LIMIT (D4h)” on page 62.
OUTPUT OVERVOLTAGE FAULT
The ISL78229 monitors the FB pin voltage to detect if output
overvoltage fault (VOUT_OV) occurs. This fault detection is active
at the beginning of soft-start (t₅ as shown in the Figure 67 on
page 30).
If the FB pin voltage is higher than 120% (default) of the voltage
regulation reference VREF_DAC, the VOUT_OV comparator is
triggered to indicate VOUT_OV fault and the PGOOD pin will be
pulled low. The corresponding bit (VOUT_OV, Bit [7]) in the
FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h)
and SALERT Signal” on page 34 and Table 3 on page 41) is set to
1 and the SALERT pin is pulled low.
At the same time, when a VOUT_OV fault condition is triggered,
since the VOUT_OV fault protection response is enabled by
default as the VOUT_OV bit (Bit [7]) is set 0 by default in the
FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK
(D1h)” on page 35 and Table 3 on page 41), the ISL78229 will
respond with fault protection actions to shut down the PWM
switching and enters either Hiccup or Latch-off mode as
described in “Fault Response Register SET_FAULT_RESPONSE
(D2h)” on page 35 and Table 3 on page 41.
The VOUT_OV fault protection can be disabled by setting the
VOUT_OV bit (Bit [7]) in “Fault Mask Register FAULT_MASK (D1h)”
on page 35 to 1 via PMBus™. If disabled, there will be no fault
protection actions when VOUT_OV fault is triggered, and the
ISL78229 will keep PWM switching and normal operation.
Under the selection of VOUT_OV fault protection activated with
Hiccup response, when the output voltage falls down to be lower
than the VOUT_OV threshold 120% VREF_DAC minus 4%
hysteresis, the device will return to normal switching through
Hiccup soft-start. The PGOOD pin will be released to be pulled
HIGH after 0.5ms delay. However, as described in the “Fault Flag
Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the
bit = 1 status in the FAULT_STATUS register will not be
automatically cleared/reset to 0 by the device itself and the
SALERT pin is kept low. The bits in the FAULT_STATUS register
can only be cleared to 0 by a Write command, or CLEAR_FAULTS
command via PMBus™, or EN/POR recycling. When all the bits in
the FAULT_STATUS register are 0, the SALERT pin is released to
be pulled HIGH.
The VOUT_OV threshold values can be set to 8 options based on
percentage of the reference VREF_DAC via PMBus™ command
“VOUT_OV_FAULT_LIMIT (D3h)” on page 61.
OVERCURRENT LIMITING AND FAULT PROTECTION
The ISL78229 has multiple levels of overcurrent protection. Each
phase is protected from an overcurrent condition by limiting its
peak current and the combined total current is protected on an
average basis. Also, each phase is implemented with
cycle-by-cycle negative current limiting (OC_NEG_TH = -48µA).
Peak Current Cycle-by-Cycle Limiting (OC1)
Each individual phase’s inductor peak current is protected with
cycle-by-cycle peak current limiting (OC1) without triggering
Hiccup or Latch-off shutdown of the IC. The controller
continuously compares the CSA output current sense signal
I_SENx (calculated by Equation 11 on page 32) to an overcurrent
limiting threshold (OC1_TH = 80µA) in every cycle. When I_SENx
reaches 80µA, the respective phase’s LGx is turned off to stop
inductor current further ramping up. In such a way, peak current
cycle-by-cycle limiting is achieved.
The equivalent cycle-by-cycle peak inductor current limiting for
OC1 can be calculated by Equation 18:
I_OC1x = 80  10^–6  _R-^R----_SS----_EE----_NT----^xx- A
(EQ. 18)
Negative Current Cycle-by-Cycle Limiting (OC_NEG)
Each individual phase’s inductor current is protected with
cycle-by-cycle negative current limiting (OC_NEG) without
triggering Hiccup or Latch-off shutdown of the IC. The controller
continuously compares the CSA output current sense signal
I_SENx (calculated by Equation 11 on page 32) to a negative
current limiting threshold (OC_NEG_TH = -48µA) in every cycle.
When I_SENx falls below -48µA, the respective phase’s UGx is
turned off to stop the inductor current further ramping down. In
such a way, negative current cycle-by-cycle limiting is achieved.
The equivalent negative inductor current limiting level can be
calculated by Equation 19:
I_OCNEGx = –48  10^–6  _R-^R----_SS----_EE----_NT----^xx- A
(EQ. 19)
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FN8656.3
February 12, 2016