ISL78229 Datasheet, PDF (39/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
External Over-Temperature Fault (OT_NTC_FAULT)
If V_NTC is lower than 300mV (default as determined by
OT_NTC_FAULT_LIMIT register), the OT_NTC_FAULT fault event is
triggered. The corresponding bit (OC_NTC_FAULT, Bit [3]) in the
FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h)
and SALERT Signal” on page 34 and Table 3 on page 41) is set to
1 and the SALERT pin is pulled low to deliver a warning to the
host.
When the OT_NTC_FAULT fault condition is triggered, since the
OT_NTC_FAULT fault protection response is disabled by default as
the OT_NTC_FAULT bit (Bit [3]) is set 1 by default in the
FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK
(D1h)” on page 35 and Table 3 on page 41), the ISL78229 will
not respond with fault protection actions and the ISL78229
continues switching and regulating normally.
The OT_NTC_FAULT fault protection can be enabled by setting the
OT_NTC_FAULT bit (Bit [3]) in “Fault Mask Register FAULT_MASK
(D1h)” on page 35 to 0 via PMBus™. If enabled, the ISL78229
will respond with fault protection actions to shut down the PWM
switching and enters either Hiccup or Latch-off mode as
described in “Fault Response Register SET_FAULT_RESPONSE
(D2h)” on page 35 and Table 3 on page 41.
Under the selection of OT_NTC_FAULT fault protection activated
with a Hiccup response, when the temperature drops and V_NTC
rises back to be above 300mV (default), the OT_NTC_FAULT is no
longer tripped, and the device will return to normal switching
through Hiccup soft-start. However, as described in the “Fault Flag
Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the
bit = 1 status in the FAULT_STATUS register will not be
automatically cleared/reset to 0 by the device itself and the
SALERT pin is kept low. The bits in the FAULT_STATUS register
can only be cleared to 0 by a Write command, or CLEAR_FAULTS
command via PMBus™, or EN/POR recycling. When all the bits in
the FAULT_STATUS register are 0, the SALERT pin is released to
be pulled HIGH.
The OT_NTC_FAULT threshold values can be set to different
values via PMBus™ command “OT_NTC_FAULT_LIMIT (4Fh)” on
page 50.
This warning detection is active at the beginning of soft-start (t₅
as shown in the Figure 67 on page 30).
INTERNAL DIE OVER-TEMPERATURE PROTECTION
The ISL78229 PWM will be disabled if the junction temperature
reaches +160°C (typical) while the internal LDO is alive to keep
PVCC/VCC biased (VCC connected to PVCC). A +15°C hysteresis
ensures that the device will restart with soft-start when the
junction temperature falls below +145°C (typical).
Internal 5.2V LDO
ISL78229 has an internal LDO with input at VIN and a fixed
5.2V/100mA output at PVCC. The internal LDO tolerates an input
supply range of VIN up to 55V (60V absolute maximum). A 10µF,
10V or higher X7R type of ceramic capacitor is recommended
between PVCC to GND. At low VIN operation when the internal
LDO is saturated, the dropout voltage from the VIN pin to the
PVCC pin is typically 0.3V under 80mA load at PVCC as shown in
the “Electrical Specifications” table on page 9. This is one of the
constraints to estimate the required minimum VIN voltage.
The output of this LDO is mainly used as the bias supply for the
gate drivers. With VCC connected to PVCC as in the typical
application, PVCC also supplies other internal circuitry. To provide
a quiet power rail to the internal analog circuitry, it is
recommended to place an RC filter between PVCC and VCC. A
minimum of 1µF ceramic capacitor from VCC to ground should
be used for noise decoupling purpose. Since PVCC is providing
noisy drive current, a small resistor like 10Ω or smaller between
the PVCC and VCC helps to prevent the noises interfering from
PVCC to VCC.
Figure 72 shows the internal LDO’s output voltage (PVCC)
regulation versus its output current. The PVCC will drop to 4.5V
(typical) when the load is 195mA (typical) because of the LDO
current limiting circuits. When the load current further increases,
the voltage will drop further and finally enter current foldback
mode where the output current is clamped to 100mA (typical). At
the worst case when LDO output is shorted to ground, the LDO
output is clamped to 100mA.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.00
0.05
0.10
0.15
IOUT_PVCC (A)
0.20
0.25
FIGURE 72. INTERNAL LDO OUTPUT VOLTAGE vs LOAD
Based on the junction to ambient thermal resistance R_JA of the
package, the maximum junction temperature should be kept below
+125°C. However, the power losses at the LDO need to be
considered, especially when the gate drivers are driving external
MOSFETs with large gate charges. At high V_IN, the LDO has
significant power dissipation that may raise the junction
temperature where the thermal shutdown occurs.
With an external PNP transistor as shown in Figure 73 on
page 40, the power dissipation of the internal LDO can be moved
from the ISL78229 to the external transistor. Choose R_S to be
68Ω so that the LDO delivers about 10mA when the external
transistor begins to turn on. The external circuit increases the
minimum input voltage to approximately 6.5V.
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FN8656.3
February 12, 2016