ISL78229 Datasheet, PDF (68/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
If R_OEA>>R_CP, C_CP1>>C_CP2, and R_OEA = infinite, the equation
can be simplified as shown in Equation 46:
H_e2s
=
g_m  _s-----_---_C-----_C----¹_P----₁-+---_-^s--_---₁^---^R-+----^C-_s---^P--_---^_R---^C-_C---^C--_P---^P--_-¹--_C----_C----_P----₂----_
=
1 + ----^s-----
-^--_s--¹-  -₁----+-------^_------s--^z_------²_--
_p2
(EQ. 46)
Where:
_p2 = _C----^g-_C---^m-_P----₁-
_z2 = _R-----_C----_P-----_-¹--_C-----_C----_P----₁-
_p3 = -_R----_C----_P-----_-¹--_C-----_C----_P----₂-
If Type-3 compensation is needed, the transfer function at the
feedback resistor network is:
H_e1S = -_R----_F----_B--^R--₁---^F-+--^B---_R-¹---_F----_B----₂-  ₁-¹----++-----_--^{----------ss}_{---pz---------}¹¹_---
(EQ. 47)
Where:
_z1 = -_C----₁-----_---_--_R-----_F--¹-_B----₂----+-----_R-----₁----_
_p1 = _C-----₁-----_---_R---------F--------_B--------₂--------_------_R----------_F------_B--------₁--_R--------+--_F------_B-_R----¹_---2--_F-------+-_B-------_2-R--------_--_F----_R---_{B------1--1-------+----------R}--------_F--------_B--------₁--------_------_R----------₁--
The total transfer function with compensation network and gain
stage will be expressed:
G_opens = G_vcvos  H_e1s  H_e2s
(EQ. 48)
Use f = ω/2π to convert the pole and zero expressions to
frequency domain, and from Equations 42, 47 and 48, select the
compensator’s pole and zero locations.
In general, as described earlier, a Type-2 compensation is
enough. Typically the crossover frequency is set 1/5 to 1/3 of the
ω_RHZ frequency. For the compensator as general rule, set
ω_p2/2π at very low end frequency; set ω_z2/2π at 1/5 of the
crossover frequency; set ω_p3/2π at the ESR zero or the RHZ
frequency ω_RHZ/2π, whichever is lower.
VCC Input Filter
To provide a quiet power rail to the internal analog circuitry, it is
recommended to place an RC filter between PVCC and VCC. A
10Ω resistor between PVCC and VCC and at least 1µF ceramic
capacitor from VCC to GND are recommended.
Current Sense Circuit
To set the current sense resistor, the voltage across the current
sense resistor should be limited to within ±0.3V. In a typical
application, it is recommended to set the voltage across the
current sense resistor between 30mV to 100mV for the typical
load current condition.
Layout Considerations
For DC/DC converter design, the PCB layout is very important to
ensure the desired performance.
1. Place input ceramic capacitors as close as possible to the IC's
VIN and PGND/SGND pins.
2. Place the output ceramic capacitors as close as possible to
the power MOSFET. Keep this loop (output ceramic capacitor
and MOSFETs for each phase) as small as possible to reduce
voltage spikes induced by the trace parasitic inductances
when MOSFETs switching ON and OFF.
3. Place the output aluminum capacitors close to power
MOSFETs too.
4. Keep the phase node copper area small but large enough to
handle the load current.
5. Place the input aluminum and some ceramic capacitors close
to the input inductors and power MOSFETs.
6. Place multiple vias under the thermal pad of the IC. The
thermal pad should be connected to the ground copper plane
with as large an area as possible in multiple layers to
effectively reduce the thermal impedance. Figure 77 shows
the layout example for vias in the IC bottom pad.
FIGURE 77. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE
IC BOTTOM PAD
7. Place the 10µF decoupling ceramic capacitor at the PVCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
8. Place the 1µF decoupling ceramic capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
9. Keep the bootstrap capacitor as close as possible to the IC.
10. Keep the driver traces as short as possible and with relatively
large width (25mil to 40 mil is recommended), and avoid
using vias or a minimal number of vias in the driver path to
achieve the lowest impedance.
11. Place the current sense setting resistors and the filter
capacitor (shown as R_SETxB, R_BIASxB and C_ISENx in Figure 69
on page 32) as close as possible to the IC. Keep each pair of
the traces close to each other to avoid undesired switching
noise injections.
12. The current sensing traces must be laid out very carefully
since they carry tiny signals with only tens of mV.
For the current sensing traces close to the power sense resistor
(R_SENx), the layout pattern shown in Figure 78 is recommended.
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FN8656.3
February 12, 2016