ISL78229 Datasheet, PDF (35/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
After the ISL78229 is enabled, during the part initializing time
t₁ - t₄ (refer to Figure 67 on page 30) before soft-start, the
SALERT pin is kept pulled low. If no faults (listed in Table 4 on
page 41) occurs during t₁ - t₄, the SALERT pin open-drain
transistor will be open at t₄ when soft-start begins and the pin
voltage is pulled high by the external pull-up circuits. If any fault
in Table 4 on page 41 occurs after the beginning of soft-start, the
corresponding bit of the FAULT_STATUS register will be set to 1
and the SALERT pin will be pulled low.
Only when all the FAULT_STATUS register bits are 0, the SALERT
pin can be released to be pulled HIGH.
Fault Mask Register FAULT_MASK (D1h)
When any of the faults in Table 4 on page 41 are detected, the
device will respond with either protecting actions (Hiccup or
Latch-off) or ignoring this fault depending on the corresponding
bit setting of the FAULT_MASK register (“FAULT_MASK (D1h)” on
page 59).
Each bit of this register controls one specific fault condition to be
ignored or not (refer to list in Table 4 on page 41). The bit values
are defined as follows:
• Bit = 1 means to ignore, no protection action taken for the
triggered fault, and the ISL78229 keeps its normal PWM
switching and operations.
• Bit = 0 means to respond with protecting action to enter either
Hiccup or Latch-off as fault response as described in “Fault
Response Register SET_FAULT_RESPONSE (D2h)”.
The register FAULT_MASK has a default setting and can be
programmed via PMBus™ command “FAULT_MASK (D1h)” on
page 59 to set a specific fault’s protection response to be ignored
or not. At default, the VOUT_UV fault is ignored with Bit [6] set to
1 as default.
Refer to PMBus™ command “FAULT_MASK (D1h)” on page 59 for
the details and Table 3 on page 41 for fault related registers
summary.
Fault Response Register SET_FAULT_RESPONSE (D2h)
The fault response for each type of fault protection (listed in
Table 4 on page 41) can be programmed to be either Hiccup or
Latch-off by setting the corresponding bit of the register
SET_FAULT_RESPONSE (refer to PMBus™ command
“SET_FAULT_RESPONSE (D2h)” on page 60 and Table 3 on
page 41).
• When bit = 1, the fault protection response is Hiccup mode
• When bit = 0, the fault protection response is Latch-off mode
The default bit values are determined by the HIC/LATCH pin
configuration as listed in the following. Each bit value can be
changed via PMBus™ to set the respective bit of the fault response
register (SET_FAULT_RESPONSE) at default:
• When the HIC/LATCH pin is pulled high (VCC), the fault response
will be Hiccup mode.
• When the HIC/LATCH pin is pulled low (GND), the fault response
will be Latch-off mode.
In Hiccup mode, the device will stop switching when a fault
condition is detected, and restart from soft-start after
500ms (typical). This operation will be repeated until fault
conditions are completely removed.
In Latch-off mode, the device will stop switching when a fault
condition is detected and PWM switching being kept off even
after fault conditions are removed. In Latch-off status, the
internal LDO is alive to keep PVCC, and PMBus™ interface is
available for the user to monitor the type of fault triggered or
other parameters. By either toggling the EN pin or cycling
VCC/PVCC below the POR threshold will restart the system.
Refer to PMBus™ command “SET_FAULT_RESPONSE (D2h)” on
page 60 for details and Table 3 on page 41 for fault related
registers summary.
INPUT OVERVOLTAGE FAULT
As shown in Figure 3 on page 7, the ISL78229 monitors the VIN
pin voltage divided by 48 (VIN/48) as the input voltage
information. This fault detection is active at the beginning of
soft-start (t₅ as shown in Figure 67 on page 30).
The VIN_OV comparator compares VIN/48 to 1.21V reference to
detect if VIN_OV fault is triggered. Equivalently, when V_IN >58V
(for 5µs), VIN_OV fault event is triggered. The PGOOD pin will be
pulled low and the corresponding bit (VIN_OV, Bit [2]) in the
FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h)
and SALERT Signal” on page 34 and Table 3 on page 41) is set to
1 and the SALERT pin is pulled low.
At the same time the VIN_OV fault condition is triggered, since
the VIN_OV fault protection response is enabled by default as the
VOIN_OV bit (Bit [2]) is set 0 by default in the FAULT_MASK
register (refer to “Fault Mask Register FAULT_MASK (D1h)” on
page 35 and Table 3 on page 41), the ISL78229 will respond with
fault protection actions to shut down the PWM switching and
enters either Hiccup or Latch-off mode as described in “Fault
Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and
Table 3 on page 41.
The VIN_OV fault protection can be disabled by setting the
VIN_OV bit (Bit [2]) in “Fault Mask Register FAULT_MASK (D1h)” on
page 35 to 1 via PMBus™. If disabled, there will be no fault
protection actions when VIN_OV fault is triggered, and the
ISL78229 will keep PWM switching and normal operation.
Under the selection of VIN_OV fault protection activated with
Hiccup response, when the output voltage falls down to be lower
than the VIN_OV threshold 58V, the device will return to normal
switching through Hiccup soft-start. PGOOD will be released to be
pulled HIGH after a 0.5ms delay. As described in “Fault Flag
Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the
bit = 1 status in the FAULT_STATUS register will not be
automatically cleared/reset to 0 by the device itself and the
SALERT pin is kept low. The bits in the FAULT_STATUS register
can only be cleared to 0 by a Write command, or CLEAR_FAULTS
command via PMBus™, or EN/POR recycling. When all the bits in
the FAULT_STATUS register are 0, the SALERT pin is released to
be pulled HIGH.
OUTPUT UNDERVOLTAGE FAULT
The ISL78229 monitors the FB pin voltage to detect if output
undervoltage fault (VOUT_UV) occurs.
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FN8656.3
February 12, 2016