ISL78229 Datasheet, PDF (31/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
t₆ - t₇: At t₆ COMP is above the current sense ramp offset and the
drivers start switching. Output voltage ramps up while FB voltage
is following SS ramp during this soft-start period. At t₇, output
voltage reaches the regulation level and FB voltage reaches 1.6V
(VREF_DAC Default).
t₇ - t₈: SS continues ramping up until it reaches SS clamp voltage
(V_SSPCLAMP) 3.47V at t₈ indicating the SS pin ramp-up is
completed. At t₈, the ISL78229 generates an internal SS_DONE
signal, which goes HIGH when both V_SSPIN = V_SSPCLAMP (3.47V)
and VREF_TRK ≥ 0.3V (as shown in Figure 3 on page 7). This
indicates the soft-start has completed.
t₈ - t₉: After t₈, a delay time of either 0.5ms or 100ms is inserted
before the PGOOD pin is released HIGH at t₉ depending on the
selected mode (refer to Table 2 on page 34).
1. If the DE/PHDRP pin = GND or FLOAT to have DE mode
selected, the PGOOD rising delay from V_SSPIN = V_SSPCLAMP
(3.47V) AND VREF_TRK ≥0.3V to PGOOD rising is 0.5ms.
2. If the DE/PHDRP pin = GND to have CCM mode selected, the
PGOOD rising delay from V_SSPIN = V_SSPCLAMP (3.47V) and
VREF_TRK ≥0.3V to PGOOD rising is 100ms, during which
period, the device is transitioning from DE mode to CCM
mode. The high-side gate UGx is controlled to gradually
increase the ON time to finally merged with CCM ON-time.
This synchronous MOSFET “soft-ON” feature is unique and
ensures smooth transition from DCM mode to CCM mode
after soft-start completes. More importantly, this “SYNC FET
soft-ON” function eliminates the large negative current, which
usually occurs when starting up to a high prebiased output
voltage. This feature makes the system robust for all the
challenging start-up conditions and greatly improves the
system reliability.
Enable
To enable the device, the EN pin needs to be driven higher than
1.2V (typical) by the external enable signal or resistor divider
between VIN and GND. The EN pin has an internal 5MΩ (typical)
pull-down resistor. Also, this pin internally has a 5.2V (typical)
clamp circuit with a 5kΩ (typical) resistor in series to prevent
excess voltage applied to the internal circuits. When applying the
EN signal using resistor divider from VIN, internal pull-down
resistance needs to be considered. Also, the resistor divider ratio
needs to be adjusted as its EN pin input voltage may not exceed
5.2V.
To disable or reset all fault status, the EN pin needs to be driven
lower than 1.1V (typical). When the EN pin is driven low, the
ISL78229 turns off all of the blocks to minimize the off-state
quiescent current.
VIN
EN
FROM
EXTERNAL
EN CONTROL
5k
5M
VCC
+
5.2V
CLAMP
-
TO INTERNAL
CIRCUITS
1.2V
Soft-Start
FIGURE 68. ENABLE BLOCK
Soft-start is implemented by an internal 5µA current source
charging the soft-start capacitor (C_SS) at SS to ground. The
voltage on the SS pin slowly ramps up as the reference voltage
for the FB voltage to follow during soft-start.
Typically, for boost converter before soft-start, its output voltage
is charged up to be approximately a diode drop below the input
voltage through the upper side MOSFETs’ body diodes. To more
accurately correlate the soft-start ramp time to the output
voltage ramp time, the ISL78229 SS pin voltage is prebiased
with voltage equal to FB before soft-start begins. The soft-start
ramp time for the boost output voltage ramping from V_IN to the
final regulated voltage V_OUTreg, can be calculated by Equation 7,
where V_REF is typically the VREF_DAC voltage (1.6V default) with
the TRACK pin tied HIGH:
t_SS
=
V_R
E
F

1

–
V^-----_O^---V-_U^---I-_T^-N---_r^--_e^----_g^-

C_{-5----S---A-S--}
(EQ. 7)
PGOOD Signal
The PGOOD pin is an open-drain logic output to indicate that the
soft-start period is completed, the input voltage is within safe
operating range and the output voltage is within the specified
range. The PGOOD comparator monitors the FB pin to check if
output voltage is within 80% to 120% of reference voltage
VREF_DAC (1.6V default).
As described at the t₈ - t₉ duration in “Operation Initialization
and Soft-Start” on page 30, the PGOOD pin is pulled low during
soft-start and it’s released HIGH after SS_DONE with a 0.5ms or
100ms delay.
PGOOD will be pulled low if any of the comparators for FB_UV,
FB_OV or VIN_OV is triggered for a duration longer than 10µs.
In normal operation after start-up, under fault recovery, the
PGOOD will be released high with the same 0.5ms delay time
after the fault is removed.
Current Sense
The ISL78229 peak current control architecture senses the
inductor current continuously for fast response. A sense resistor
is placed in series with the power inductor for each phase, and
the ISL78229 Current Sense Amplifiers (CSA) continuously sense
the respective inductor current as shown in Figure 69 by sensing
the voltage signal across the sense resistor R_SENx (where “x”
indicates the specific phase number and same note applied
throughout this document). The sensed current for each active
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FN8656.3
February 12, 2016