ISL78229 Datasheet, PDF (25/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
Operation Description
The ISL78229 is a 2-phase synchronous boost controller with
integrated drivers. It supports wide input and output ranges of 5V
to 55V during normal operation and the VIN pin withstands
transients up to 60V.
The ISL78229 is integrated with 2A sourcing/3A sinking strong
drivers to support high efficiency and high current synchronous
boost applications. The drivers have a unique feature of adaptive
dead time control of which the dead time can be programmed
for different external MOSFETs, achieving both optimized
efficiency and reliable MOSFET driving. The ISL78229 has
selectable diode emulation and phase dropping functions for
enhanced light-load efficiency.
The PWM modulation method is a constant frequency Peak
Current Mode Control (PCMC), which has benefits of input voltage
feed-forward, a simpler loop to compensate compared to voltage
mode control and inherent current sharing capability.
The ISL78229 offers a track function with unique features of
accepting either digital or analog signals for the user to adjust
reference voltage externally. The digital signal track function
greatly reduces the complexity of the interface circuits between
the central control unit and the boost regulator. Equipped with
cycle-by-cycle positive and negative current limiting, the track
function can be reliably facilitated to achieve an envelope
tracking feature in audio amplifier applications, which
significantly improves system efficiency.
In addition to the cycle-by-cycle current limiting, the ISL78229 is
implemented with a dedicated average Constant Current (CC) loop
for input current. For devices having only peak current limiting, the
average current under peak current limiting varies quite largely
because the inductor ripple varies with changes of V_IN and V_OUT
and tolerances of f_SW and inductors. The ISL78229’s unique CC
feature is able to have the average input current accurately
controlled to be constant without shutdown. Under certain
constant input voltage, this means constant power limiting, which
is especially useful for the boost converter. It helps the user
optimize the system with the power devices’ capability fully utilized
by well controlled constant input power.
With the PMBus™ compliant digital interface, the ISL78229
provides the designer access to a number of useful system
control parameters and diagnostic features.
Details of the functions are described in the following sections.
Synchronous Boost
In order to improve efficiency, the ISL78229 employs
synchronous boost architecture as shown in Figure 4 on page 8.
The UGx output drives the high-side synchronous MOSFET, which
replaces the freewheeling diode and reduces the power losses
due to the voltage drop of the freewheeling diode.
While the boost converter is operating in steady state Continuous
Conduction Mode (CCM), each phase’s low-side MOSFET is
controlled to turn on with duty cycle D and ideally the upper
MOSFET will be ON for (1-D). Equation 1 shows the input to
output voltage DC transfer function for boost is:
V_OUT = ₁--^V---–--^I--^N-_D---
(EQ. 1)
DRIVER CONFIGURATION
As shown in Figure 4 on page 8, the upper side UGx drivers are
biased by the C_BOOTx voltage between BOOTx and PHx (where “x”
indicates the specific phase number and same note applied
throughout this document). C_BOOTx is charged by a charge pump
mechanism. PVCC charges BOOTx through the Schottky diode
D_BOOTx when LGx is high pulling PHx low. BOOTx rises with PHx
and maintains the voltage to drive UGx as the D_BOOTx is reverse
biased.
At start-up, the charging to C_BOOTx from 0 to ~4.5V will cause
PVCC to dip a little. So a typical 5.1Ω resistor R_PVCCBT is
recommended between PVCC and D_BOOTx to prevent PVCC from
falling below VPORL_PVCC. The typical value for C_BOOTx is
0.47µF.
The BOOTx to PHx voltage is monitored by UVLO circuits. When
BOOTx-PHx falls below a 3V threshold, the UGx output is disabled.
When BOOTx-PHx rises back to be above this threshold plus
150mV hysteresis, the high-side driver output is enabled.
For standard boost application when upper side drivers are not
needed, both UG1 and UG2 can be disabled by connecting either
BOOT1 or BOOT2 to ground before part start-up initialization. PHx
should be connected to ground.
PROGRAMMABLE ADAPTIVE DEAD TIME CONTROL
The UGx and LGx drivers are designed to have an adaptive dead
time algorithm that optimizes operation with varying operating
conditions. In this algorithm, the device detects the off timing of
LGx (UGx) voltages before turning on UGx (LGx).
Furthermore, the dead time between UGx ON and LGx ON can be
programmed by the resistor at the RDT pin. The typical range of
programmable dead time is 55ns to 200ns, or larger. This is
intended for different external MOSFETs applications to adjust
the dead time, maximizing the efficiency while at the same time
preventing shoot-through. Refer to Figure 59 on page 26 for the
selection of the RDT resistor and dead time, where t_DT1 refers to
the dead time between UG Falling to LG rising, and t_DT2 refers to
the dead time between LG Falling to UG rising. The dead time is
smaller with a lower value RDT resistor, and it’s clamped to
minimum 57ns when RDT is shorted to ground. Since a current
as large as 4mA will be pulled from the RDT pin if the RDT pin is
shorted to ground, it is recommended to use 5kΩ as the smallest
value for the RDT resistor where the current drawing from the
RDT pin is 0.5V/5kΩ = 100µA.
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FN8656.3
February 12, 2016