ISL78229 Datasheet, PDF (5/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
Functional Pin Description (Continued)
PIN NAME
PLLCOMP
EN
CLKOUT
BOOT2
UG2
PH2
LG2
PGND
PVCC
LG1
PH1
UG1
BOOT1
VIN
ISEN1N
ISEN1P
ISEN2N
ISEN2P
NC
PIN #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DESCRIPTION
This pin serves as the compensation node for the switching frequency clock’s PLL (Phase Lock Loop). A second order
passive loop filter connected between this pin and ground compensates the PLL loop. Refer to “Oscillator and
Synchronization” on page 29 for more details.
This pin is a threshold-sensitive enable input for the controller. When the EN pin is driven above 1.2V, the ISL78229 is
enabled and the internal LDO is activated to power up PVCC followed by a start-up procedure. Driving the EN pin below
0.95V will disable the IC and clear all fault states. Refer to “Enable” on page 31 for more details.
This pin outputs a clock signal with same frequency to one phase’s switching frequency. The rising edge signal on the CLKOUT
pin is delayed by 90° from the rising edge of LG1 of the same IC. With CLKOUT connected to the FSYNC pin of the second
ISL78229, a 4-phase interleaving operation can be achieved. Refer to “Oscillator and Synchronization” on page 29 for more
details.
This pin provides bias voltage to the Phase 2 high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable
to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between
the BOOT2 and PH2 pins. In the typical configuration, PVCC is providing the bias to BOOT2 through a fast switching diode.
In applications where a high-side driver is not needed (standard boost application for example), BOOT2 is recommended
to be connected to ground. The ISL78229 IC can detect BOOT2 being grounded during start-up and both the Phase 1 and
Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
Phase 2 high-side gate driver output. This output can be disabled by tying either BOOT1 and PH1 to ground or BOOT2 and
PH2 to ground.
Connect this pin to the source of the Phase 2 high-side MOSFETs and the drain of the low-side MOSFETs. This pin
represents the return path for the Phase 2 high-side gate drive.
Phase 2 low-side gate driver output. It should be connected to the Phase 2 low-side MOSFETs’ gates.
Provides the return path for the low-side MOSFET drivers. This pin carries a noisy driving current and the traces
connecting from this pin to the low-side MOSFET source and PVCC decoupling capacitor ground pad should be as short
as possible. All the sensitive analog signal traces should not share common traces with this driver return path. Connect
this pin to the ground copper plane (wiring away from the IC instead of connecting through the IC bottom PAD) through
several vias as close as possible to the IC.
Output of the internal linear regulator that provides bias for the low-side driver, high-side driver (PVCC connected to BOOTx
through diodes) and VCC bias (PVCC and VCC are typically connected through a small resistor like 10Ω or smaller, which helps
to filter out the noises from PVCC to VCC). The PVCC operating range is 4.75V to 5.5V. A minimum 10µF decoupling ceramic
capacitor should be used between PVCC and PGND. Refer to “Internal 5.2V LDO” on page 39 for more details.
Phase 1 low-side gate driver output. It should be connected to the Phase 1 low-side MOSFETs’ gates.
Connect this pin to the source of the Phase 1 high-side MOSFETs and the drain of the low-side MOSFETs. This pin
represents the return path for the Phase 1 high-side gate drive.
Phase 1 high-side MOSFET gate drive output. This output can be disabled by tying either BOOT1 and PH1 to ground or
BOOT2 and PH2 to ground.
This pin provides bias voltage to the Phase 1 high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable
to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between
BOOT1 and PH1 pins. In typical configuration, PVCC is providing the bias to BOOT1 through a fast switching diode.
In applications where a high-side driver is not needed (for example, standard boost application), the BOOT1 is
recommended to be connected to ground. The ISL78229 IC can detect BOOT1 being grounded during start-up and both
the Phase 1 and Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
Connect supply rail to this pin. Typically, connect boost input voltage to this pin. This pin is connected to the input of the internal
linear regulator, generating the power necessary to operate the chip. The DC voltage applied to the VIN should not exceed 55V
during normal operation. VIN can withstand transients up to 60V, but in this case, the device's overvoltage protection will stop
it from switching to protect itself. Refer to “Input Overvoltage Fault” on page 35 for more details.
The ISEN1N pin is the negative potential input to the Phase 1 current sense amplifier. This amplifier continuously senses
the Phase 1 inductor current through a power current sense resistor in series with the inductor. The sensed current signal
is used for current mode control, peak current limiting, average current limiting and diode emulation.
The ISEN1P pin is the positive potential input to the Phase 1 current sense amplifier.
The ISEN2N pin is the negative potential input to the Phase 2 current sense amplifier. This amplifier continuously senses
the Phase 2 inductor current through a power current sense resistor in series with the inductor. The sensed current signal
is used for current mode control, peak current limiting, average current limiting and diode emulation.
The ISEN2P pin is the positive phase input to the Phase 2 current sense amplifier.
Not Connected - This pin is not electrically connected internally.
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5
FN8656.3
February 12, 2016