ISL78229 Datasheet, PDF (34/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
TABLE 2. CCM/DE/PH_DROP MODE SETTING (DE/PHDRP PIN)
MODE NUMBER
(NAME)
DE/PHDRP PIN
SETTING
PHASE-DROP
DE MODE
MODE
1 (DE)
VCC
Enabled
Disabled
2 (DE+PH_DROP)
FLOAT
Enabled
Enabled
3 (CCM)
GND
Disabled
Disabled
AUTOMATIC PHASE DROPPING/ADDING
When the phase drop function is enabled, the ISL78229
automatically drops or adds Phase 2 by comparing the V_IMON to
the phase dropping/adding thresholds. V_IMON is proportional to
the average input current indicating the level of the load.
The phase dropping mode is not allowed with external
synchronization.
Phase Dropping
When load current drops and V_IMON falls below 1.1V, Phase 2 is
disabled. For better transient response during phase dropping,
the ISL78229 will gradually reduce the duty cycle of the phase
from steady state to zero, typically within 8 to 10 switching
cycles. This gradual dropping scheme will help smooth the
change of the PWM signal and stabilize the system when phase
dropping happens.
From Equations 13 and 14, the phase dropping current threshold
level for the total 2-phase boost input current can be calculated
by Equation 16.
I_INphDRP = ^----^R---------^{I--1--M----.----1--O--------N-------–-----1}---⁷--_R---^-_S--¹--_E--⁰--_N-^–---⁶---^----^---⁸-----^---^R----^S----^E----^T-- A
(EQ. 16)
Phase Adding
The phase adding is decided by two mechanisms listed as
follows. Phase 2 will be added immediately if either of the 2
following conditions are met.
1. V_IMON > 1.15V, the IMON pin voltage is higher than phase
adding threshold 1.15V. The phase adding current threshold
level for the total 2-phase boost input current can be
calculated by Equation 17.
I_INphADD = ^----^R-------^{1--I----M--.--1------O--5------N-------–-----1}---⁷--_R---^-_S--¹--_E--⁰--_N-^–---⁶---^----^---⁸-----^---^R----^S----^E----^T-- A
(EQ. 17)
2. I_SENx > 80µA (OC1), individual phase current triggers OC1.
The first is similar to the phase dropping scheme. When the load
increases causing V_IMON>1.15V, Phase 2 will be added back
immediately to support the increased load demand. Since the
IMON pin normally has large RC filter and V_IMON is average
current signal, this mechanism has a slow response and is
intended for slow load transients.
The second mechanism is intended to handle the case when load
increases quickly. If the quick load increase triggers OC1
(I_SENx>80µA) in either of the 2 phases, Phase 2 will be added
back immediately.
After Phase 2 is added, the phase dropping function will be
disabled for 1.5ms. After this 1.5ms expires, the phase dropping
circuit will be activated again and Phase 2 can be dropped
automatically as usual.
DIODE EMULATION AT LIGHT LOAD CONDITION
When the Diode Emulation mode (DE) is selected to be enabled
(Mode 1 and 2 in Table 2), the ISL78229 has cycle-by-cycle diode
emulation operation at light load achieving Discontinuous
Conduction Mode (DCM) operation. With DE mode operation,
negative current is prevented and the conduction loss is reduced,
therefore high efficiency can be achieved at light load conditions.
Diode emulation occurs during t₅-t₈ (on Figure 67 on page 30),
regardless of the DE/PHDRP operating modes (Table 2).
PULSE SKIPPING AT DEEP LIGHT-LOAD CONDITION
If the converter enters diode emulation mode and the load is still
reducing, eventually pulse skipping will occur to increase the
deep light-load efficiency. Either Phase 1 or Phase 2, or both, will
be pulse skipping at these deep light-load conditions.
Fault Protections/Indications
The ISL78229 is implemented with comprehensive fault
protections, the majority of which can be monitored and
programmed via PMBus™.
FAULTS/WARNINGS MANAGEABLE VIA PMBUS™
Table 3 on page 41 summarizes all the type of faults/warnings
accessible via PMBus™ and the 3 related registers to monitor the
fault status, enable/disable fault protecting reactions and
program the desired type of fault responses (Hiccup or Latch-off).
Refer to section “PMBus™ User Guide” starting on page 40 for
more details of the commands related to fault management.
Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal
When any of the faults in Table 3 on page 41 occurs, the
corresponding bit of FAULT_STATUS register (“FAULT_STATUS
(D0h)” on page 58) is set to 1 and the SALERT pin is pulled low,
regardless if that type of fault is masked by the corresponding bit
in the FAULT_MASK register.
The bits of the FAULT_STATUS register status are kept unchanged
as long as PVCC/VCC and EN are HIGH. Even when the fault
conditions are gone, the bit = 1 status will not be automatically
cleared/reset to 0 by the device itself.
Each individual or multiple bits can be cleared/reset to 0, but
only by a Write command, or a CLEAR_FAULTS command via the
PMBus™, or EN/POR recycling.
Refer to “FAULT_STATUS (D0h)” on page 58 for more details of this
PMBus™ command, and Table 3 on page 41 for fault related
registers summary.
SALERT Pin
The SALERT pin is an open-drain logic output and should be
connected to VCC through a typical 10k resistor. When any bit of
FAULT_STATUS register is set to 1, the SALERT pin will be pulled
low, regardless if that type of fault is masked by the
corresponding bit in the FAULT_MASK register. The host is
interrupted by SALERT signal and then inquire the ISL78229 via
PMBus™ for informations about the faults/warnings recorded in
the FAULT_STATUS register or any others to diagnose.
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FN8656.3
February 12, 2016