ISL78229 Datasheet, PDF (38/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
Average Overcurrent Fault (OC_AVG)
The ISL78229 monitors the IMON pin voltage (which represents
the average current signal) to detect if Average Overcurrent
(OC_AVG) fault occurs. As shown in Figure 3 on page 7, the
comparator CMP_OCAVG compares V_IMON to 2V (as default)
threshold. This fault detection is active at the beginning of
soft-start (t₅ as shown in Figure 67 on page 30).
When V_IMON is higher than 2V, the OC_AVG fault is triggered. The
corresponding bit (OC_AVG, Bit [4]) in the FAULT_STATUS register
(“Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on
page 34 and Table 3 on page 41) is set to 1 and the SALERT pin
is pulled low.
The fault response at default is either Hiccup or Latch-off (as
described in “Fault Response Register SET_FAULT_RESPONSE
(D2h)” on page 35).
At the same time when an OC_AVG fault condition is triggered,
since the OC_AVG fault protection response is enabled by default
as the OC_AVG bit (Bit [4]) is set 0 by default in the FAULT_MASK
register (refer to “Fault Mask Register FAULT_MASK (D1h)” on
page 35 and Table 3 on page 41), the ISL78229 will respond with
fault protection actions to shut down the PWM switching and
enters either Hiccup or Latch-off mode as described in “Fault
Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and
Table 3 on page 41.
The OC_AVG fault protection can be disabled by setting the
OC_AVG bit (Bit [4]) in “Fault Mask Register FAULT_MASK (D1h)” on
page 35 to 1 via PMBus™. If disabled, there will be no fault
protection actions when OC_AVG fault is triggered and the device
will keep PWM switching and normal operation.
Under the selection of OC_AVG fault protection activated with
Hiccup response, when the IMON voltage falls down to be lower
than the 2V (default) threshold, the device will return to normal
switching through Hiccup soft-start. As described in the “Fault
Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34,
the bit = 1 status in the FAULT_STATUS register will not be
automatically cleared/reset to 0 by the device itself and the
SALERT pin is kept low. The bits in the FAULT_STATUS register
can only be cleared to 0 by a Write command, or CLEAR_FAULTS
command via PMBus™, or EN/POR recycling. When all the bits in
the FAULT_STATUS register are 0, the SALERT pin is released to
be pulled HIGH.
The OC_AVG fault threshold can be set to 8 options via PMBus™
command “OC_AVG_FAULT_LIMIT (D6h)” on page 64.
EXTERNAL TEMPERATURE MONITORING AND
PROTECTION (NTC PIN)
The NTC pin allows temperature monitoring with a Negative
Temperature Coefficient (NTC) thermistor connected from this
pin to ground. An accurate 20µA current sourcing out of the NTC
pin develops a voltage across the NTC thermistor, which can be
converted to the Celsius temperature due to the NTC thermistor
characteristic. A precision resistor (100k, 0.1% for example) can
be put in parallel with the NTC thermistor to linearize the voltage
versus temperature ratio in certain range.
As an example, to use a 100k resistor in parallel with an NTC
thermistor NTCS0805E3474FXT on the NTC pin, Figure 71 shows
the curve of the NTC pin voltage versus the temperature. The user
can read the NTC pin voltage over PMBus™ and converts the
voltage to temperature using the curve in the chart.
In the board layout, the NTC resistor should be placed in the area
that needs the temperature to be monitored. Typically the NTC is
placed close to the power devices like MOSFETs to monitor the
board temperature close to them.
The voltage on the NTC pin is monitored for over-temperature
warning (OT_NTC_WARN) and over-temperature fault
(OT_NTC_FAULT), both flagged by SALERT. The default threshold
for OT warning is 450mV and the default threshold for OT fault is
300mV. Both thresholds can be changed to different values via
PMBus™ commands “OT_NTC_WARN_LIMIT (51h)” on page 51
and “OT_NTC_FAULT_LIMIT (4Fh)” on page 50.
If NTC function is not used, the NTC pin should be connected to
VCC.
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
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0
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110120 13 014 0150
TEMPERATURE (°C)
FIGURE 71. NTC VOLTAGE vs TEMPERATURE
External Over-Temperature Warning (OT_NTC_WARN)
If V_NTC is lower than 450mV (default as determined by
OT_NTC_WARN_LIMIT register), the OT_NTC_WARN warning
event is triggered. The corresponding bit (OT_NTC_WARN, Bit [1])
in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS
(D0h) and SALERT Signal” on page 34 and Table 3 on page 41) is
set to 1 and the SALERT pin is pulled low to deliver a warning to
the host. The ISL78229 continues switching and regulating
normally. There is no fault protection response when an
OT_NTC_WARN event is triggered.
When the temperature drops and V_NTC rises above 450mV
(default), the OT_NTC_WARN is no longer tripped. But as
described in the “Fault Flag Register FAULT_STATUS (D0h) and
SALERT Signal” on page 34, the bit = 1 status in the
FAULT_STATUS register will not be automatically cleared/reset to
0 by the device itself and the SALERT pin is kept low. The bits in
the FAULT_STATUS register can only be cleared to 0 by a Write
command, or CLEAR_FAULTS command via PMBus™, or EN/POR
recycling. When all the bits in the FAULT_STATUS register are 0,
the SALERT pin is released to be pulled HIGH.
The OT_NTC_WARN threshold OT_NTC_WARN_LIMIT values can
be set to different values via PMBus™ command
“OT_NTC_WARN_LIMIT (51h)” on page 51.
This warning detection is active at the beginning of soft-start (t₅
as shown in Figure 67 on page 30).
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FN8656.3
February 12, 2016