ISL78229 Datasheet, PDF(30/71 Page) Intersil Corporation – 2-Phase Boost Controller with Drivers

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ISL78229 Datasheet, PDF (30/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

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ISL78229

2. Ensure the charging of the boot capacitor during operations of

LGx operating at tMINON. One typical case is an operation

when the input voltage is close to the output voltage. The duty

cycle is smallest at tMINON and CBOOTx is charged by PVCC via

DBOOTx with short duration of tMINON minus the delay to pull

phase low. If such operation is required, especially when a

large MOSFET with large Qg is used to support heavy load

application, larger tMINON can be programmed with the

resistor at the RBLANK pin to ensure CBOOTx can be

sufficiently charged during minimum duty cycle operation.

Refer to Figure 66 for the selection of RBLANK resistor and

tMINON time. A 5kÎ© resistor is recommended as the minimum

RBLANK resistor.

500

450

400

350

300

250

200

150

100

5 10 15 20 25 30 35 40 45 50 55 60 65 70

RBLANK (kï)

FIGURE 66. tMINON vs RBLANK

Operation Initialization and Soft-Start

Prior to converter initialization, the EN pin voltage needs to be

higher than its rising threshold and the PVCC/VCC pin needs to be

higher than the rising POR threshold. When these conditions are

met, the controller begins initialization and soft-start. Figure 67

shows the ISL78229 internal start-up timing diagram from the

power-up to soft-start.

1.2V

POR_R PVCC/VCC

PLLCOMP

CLKOUT

COMP

VFB

COMP_Ramp_Offset

PGOOD

t1 t2 t3

t4t5 t6

t8 t9

FIGURE 67. CIRCUIT INITIALIZATION AND SOFT-START

Assuming input voltage is applied to the VIN pin before t1 and VCC

is connected to PVCC, as shown on Figure 67, the descriptions for

start-up procedure is elaborated in the following:

t1 - t2: The enable comparator holds the ISL78229 in shutdown

until the VEN rises above 1.2V (typical) at the time of t1. During

t1 - t2 VPVCC/VCC will gradually increase and reaches the internal

power-on reset (POR) rising threshold 4.5V (typical) at t2.

t2 - t3: During t2 - t3, the ISL78229 will go through a

self-calibration process to detect certain pin configurations

(HIC/LATCH, DE/PHDRP, ATRK/DTRAK) to latch in the selected

operation modes. The time duration for t2 - t3 is typically 195Âµs.

t3 - t4: During this period, the ISL78229 will wait until the internal

PLL circuits are locked to the preset oscillator frequency. When

PLL locking is achieved at t4, the oscillator will generate output

at the CLK_OUT pin. The time duration for t3 - t4 depends on the

PLLCOMP pin configuration. The PLL is compensated with a

series resistor-capacitor (RPLL and CPLL1) from the PLLCOMP pin

to GND and a capacitor (CPLL2) from PLLCOMP to GND. At

CPLL1 = 6.8nF, CPLL2 = 1nF. With this PLLCOMP compensation,

the time duration for t3 - t4 is around 0.7ms.

t4 - t5: The PLL locks the frequency t4 and the system is

preparing to soft-start. The ISL78229 has one unique feature to

prebias the SS pin voltage to be equal to VFB during t4 - t5, which

is around 50Âµs.

t5 - t6: At t5 the soft-start ramps up at the SS pin (VSSPIN) and the

COMP voltage starts to ramp up as well. Drivers are enabled but

not switching during t5 - t6 since the COMP is still below the

current sense ramp offset. The device operates in diode

emulation mode during soft-start period t5 - t8. The slew rate of

the SS ramp and the duration of t5 - t8 are determined by the

capacitor used at the SS pin.

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FN8656.3

February 12, 2016

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