ISL78229 Datasheet, PDF (29/71 Pages) Intersil Corporation – 2-Phase Boost Controller with Drivers

ISL78229
Oscillator and Synchronization
The switching frequency is determined by the selection of the
frequency-setting resistor, R_FSYNC, connected from the FSYNC
pin to GND. Equation 6 is provided to assist in selecting the
correct resistor value.
R_FSYNC
=
2.49
x

10  ¹⁰


0_---f-._-S5_---W-0_---5_--
–
5.5 X
10^–8_
(EQ. 6)
Where f_SW is the switching frequency of each phase. Figure 64
shows the relationship between R_FSYNC and switching frequency.
300
250
200
150
100
50
0
0 100 200 300 400 500 600 700 800 900 100 0 110 0
f SW (kHz)
FIGURE 64. f_SW vs R_FS
The ISL78229 contains a Phase Lock Loop (PLL) circuit. Refer to
Figure 4 on page 8, the PLL is compensated with a series
resistor-capacitor (R_PLL and C_PLL1) from the PLLCOMP pin to
GND and a capacitor (C_PLL2) from PLLCOMP to GND. At 300kHz
switching frequency, typical values are R_PLL = 3.24kΩ,
C_PLL1 = 6.8nF, C_PLL2 = 1nF. The PLL locking time is around
0.7ms. Generally, the same PLL compensating network can be
used in the frequency range of 50kHz to 1.1MHz. With the same
PLL compensation network, at a frequency range higher than
500kHz, the PLL loop is overcompensated. However, the PLL
loop is stable just with slow frequency response. If a faster
frequency response is required at a higher operating frequency,
the PLL compensation network can be tuned to have a faster
response. An Excel sheet to calculate the PLL compensation is
provided on the ISL78229 web page.
The ISL78229’s switching frequency can be synchronized to the
external clock signals applied at the FSYNC pin. The ISL78229
detects the input clock’s rising edge and synchronizes the rising
edge of LG1 to the input clock’s rising edge with a dead time
delay of t_DT1. The switching frequency of each phase equals the
fundamental frequency of the clock input at FSYNC. Since the
ISL78229 detects only the edge of the input clock instead of its
pulse width, the input clock’s pulse width can be as low as 20ns
(as minimum), tens of ns, or hundreds of ns depending on the
capability of the specific system to generate the external clock.
The CLKOUT pin outputs a clock signal with the same frequency
of per phase switching frequency. Its amplitude is V_CC and pulse
width is 1/12 of per phase switching period (t_SW/12). Figure 65
shows the application example to put 2 ISL78229, in parallel
with the master IC’s CLKOUT being connected to the FSYNC pin of
the slave IC for 4-phase interleaved operation. The master IC
outputs CLKOUT signal with delay of (t_SW/4-t_DT1) after
LG1_master. The slave IC FSYNC pin takes the CLKOUT_master
as the input and the slave’s IC LG1 is delayed by a time of
(35ns + t_DT1). Therefore, the LG1_slave is delayed by
(t_SW/4 + 35ns) to LG1_master which is around 90° phase shift.
With 90°phase shift between LG1 and respective LG2 for each
IC, an interleaved 4-phases with 90° phase shift boost is
achieved.
LG1_IC_Master
CLKOUT_IC_Master
tsw/4-tDT1
FSYNC_IC_Slave
LG1_IC_Slave
35ns+tDT1
t1 t2 t3
FIGURE 65. TIMING DIAGRAM OF CLKOUT vs LG1 AND FSYNC vs LG1
(CLKOUT_MASTER CONNECTED TO FSYNC_SLAVE)
Once the ISL78229 latches to be synchronized with the external
clock, if the external clock on the FSYNC pin is removed, the
switching frequency oscillator will shut down. Then the part will
detect PLL_LOCK fault (refer to Table 4 on page 41), and go to
either Hiccup mode or Latch-off mode as described in “Fault
Response Register SET_FAULT_RESPONSE (D2h)” on page 35. If
the part is set in Hiccup mode, the part will restart with frequency
set by the resistor at the FSYNC pin.
The switching frequency range of the ISL78229 set by R_FSYNC or
by synchronization is typically 50kHz to 1.1MHz.
The low end 50kHz is determined by PLL_LOCK fault protection,
which shuts down the IC when frequency is lower than 37kHz
typical (refer to Table 3 on page 41). It’s viable to operate in
frequency lower than 50kHz by masking the PLL_LOCK fault
protection through PMBus™ command “FAULT_MASK (D1h)” on
page 59.
The phase dropping mode is not allowed with external
synchronization.
MINIMUM ON-TIME (BLANK TIME) CONSIDERATION
The minimum ON-time (also called BLANK time) of LGx is the
minimum ON pulse width as long as LGx is turned ON and it is
also intended for the internal circuits to blank out the noise
spikes after LGx turns on. The t_MINON can be programmed by a
resistor at the RBLANK pin.
The selection of the t_MINON depends on 2 considerations.
1. The noise spike durations after LGx turns on, which is
normally in a range of tens of ns to 100ns or longer depending
on the external MOSFET switching characteristic and noise
coupling path to current sensing.
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FN8656.3
February 12, 2016