CD1283 Datasheet, PDF (9/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

1.0
1.1
IEEE 1284-Compatible Parallel Interface — CD1283
Overview
The CD1283 is a multi-function interface controller for printers, scanners, tape-drives, set-top
boxes, data acquisition, and other applications that require high-speed, bidirectional, parallel
communication with a host computer. All modes of the IEEE STD 1284 Standard Signaling
Method for Bidirectional Parallel Peripheral Interface for Personal Computers specification are
supported, including ECP, EPP, Reverse Byte, Reverse Nibble, and Compatible. With full support
of this standard, the CD1283 provides compatibility with all types of host parallel ports, including
older Centronics^, IBM^ PS/2^ bidirectional, and the latest IEEE 1284-compliant ports.
The dedicated state-machine design provides the fastest possible response times to all host signal
changes, with 100% guaranteed compliance to all IEEE 1284 timing, protocol, and signaling
requirements. The CD1283 device, operating at 25 MHz, has signal response times to support
2 Mbytes/sec. transfers, provided that a comparably fast host parallel port is used. This
performance headroom guarantees that the faster data rates of future host parallel port
implementations will be supported by peripheral applications using the CD1283.
In addition to the dedicated state machine, the CD1283 provides slave DMA support, and a 64-byte
FIFO to allow maximum total throughput performance. Interrupts are generated based on status
changes of the parallel port. Note, however that interrupts are not generated by FIFO threshold, or
FIFO full/empty conditions. The DMA request signal can be used to generate interrupts as long as
hardware and software implementation is handled correctly. If maximum performance is not a
requirement, the device can be monitored and controlled by polling its detailed status registers.
Another unique feature of the CD128X series of devices is the dedicated hardware for RLE
compression/decompression in ECP mode. Special logic is used to perform the ECP-RLE
compression/decompression ‘on-the-fly’ while data is moved to and from the FIFO. All of these
capabilities above and beyond the requirements of the IEEE 1284 specification permit the use of a
less expensive microprocessor by reducing the required CPU bandwidth needed for the parallel
port.
To aid in the development of hardware and software, an evaluation kit — complete with application
notes and programmer’s guide — is provided along with software examples and evaluation board
schematics. The ISA add-in card is designed to demonstrate the capabilities of the CD128X family
of devices, and enables software developers to begin testing code while the system hardware is still
in development.
Advantages
Unique Features
• Supports IEEE STD 1284 specification
• Hardware support of IEEE STD 1284 timings
• 64-byte FIFO
• Parallel port signals provide level-2 drive characteristics
• DMA channel
• ECP compression/decompression in hardware
Datasheet
9