CD1283 Datasheet, PDF (78/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
8.3
8.3.1
AC Characteristics
Asynchronous Timing
Refer to Figure 17 through Figure 25 for the reference numbers in Table 12.
(@ V_CC = 5 V ± 5%, T_A = 0°C to 70°C)
Table 12. Asynchronous Timing Reference Parameters (Sheet 1 of 2)
Timing
No.
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
t₁₇
t₁₈
t₁₉
t₂₀
t₂₁
t₂₂
t₂₃
t₂₄
Figure
Parameter
17 RESET*¹ low pulse width
19 Address setup time to CS* or DS*
19 R/W* setup time to CS* or DS*
19 Address hold time after CS*
19 R/W* hold time after CS*
19 DTACK* low to read data valid
19 DTACK* low from CS* or DS ²
19 Data bus tristate after CS* or DS* high
19 CS* or DGRANT* high from DTACK* low
19 DTACK* inactive from CS* or DGRANT* and DS* high
19 DS* high pulse width
20 Write data valid from CS* and DS* low
20 Write data hold time after DS* high
18
Clock period (T_CLK) ^{1, 3}
18
Clock low time¹
18
Clock high time ¹
21 Propagation delay, DGRANT* and DS* to DPASS*
21 Setup time, SVCACK* to DS* and DGRANT*
22 Setup time, DMAACK* to rising edge of CLK
22 Hold time, read data after rising edge of CLK
24 Setup time, write data to rising edge of CLK
19 DTACK* active pull-up time⁴
22 Data valid after falling edge of CLK (DMA read)
22 _{Hold time, DMAREQ* after DMAACK* falling edge,}
24 ^{last DMA cycle}
MIN
10
10
10
0
0
2 T_CLK
0
0
10
0
40.0
0.3 T_CLK
0.3 T_CLK
10
10
10
0
10
MAX
10
4 T_CLK + 30
30
40
1T_CLK
1000
0.7 T_CLK
0.7 T_CLK
35
30
25
1 CLK + 15
Unit
T_CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
78
Datasheet