CD1283 Datasheet, PDF (64/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
Register Name: PFHR2
Register Description: Parallel FIFO Holding Register 2
Access: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
8-Bit Character Data
Bit 2
8-Bit Hex Address: 36
Default Value: 00
Bit 1
Bit 0
These two 1-byte registers provide a data pipeline between the FIFO and DMA buffer. Data always
flows first into PFHR1, then to PFHR2 and finally, either to the FIFO or the DMABUF register.
The flow is to the FIFO if DMAdir is a ‘1’, and from the FIFO if DMAdir is ‘0’. The pipeline and
the holding registers support ‘tagged’ data for complete support of the ECP Parallel Port mode.
Tagged data is either an address code or a run-length code.
In the receive direction (if RLEen is set in the PFCR), run-length codes are captured in the RLCR
for decompression of received data. ECP address codes are recognized and pass into the PFHR1–
PFHR2 pipeline. The presence of an ECP address will interrupt DMA flow and cause an interrupt
to the host so it can remove the tagged data from the pipeline by reading either PFHR2 or PFHR1.
In the transmit direction, the host may introduce ECP address (tagged) data or run-length codes for
precompressed data by setting the setTAG bit in PFCR and writing the byte to be tagged to PFHR1.
The setTAG bit must be set prior to writing to PFHR1 for each tagged data transfer. To perform a
tagged data transfer, the automatic DMA function must be disabled prior to the transfer (set
DMAen to ‘0’). This can be done at the same time that setTAG is set to ‘1’.
These registers are cleared by device or FIFO reset and marked as empty in HRSR. Any tagged
status is also cleared.
7.3.12
Parallel FIFO Quantity Register
Register Name: PFQR
Register Description: Parallel FIFO Quantity
Access: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Data or Space Available in FIFO — Max x’40
8-Bit Hex Address: 3A
Default Value: 00
Bit 1
Bit 0
This register maintains the quantity (or count) of either data bytes or space available in the parallel
FIFO. In the receive direction (DMAdir is set to ‘0’), PFQR counts data characters in the FIFO. In
the transmit direction (DMAdir is set to ‘1’), PFQR counts space available in the FIFO for
additional characters to transmit. FIFOres together with the value of DMAdir initialize PFQR to
either x’00 (receive) or x’40 (transmit).
In either case, the PFQR indicates only the quantity of data or space available in the FIFO, and does
not include the data pipeline registers.
7.3.13
Parallel FIFO Status Register
Register Name: PFSR
Register Description: Parallel FIFO Status
Access: Read only
Bit 7
Bit 6
Bit 5
FFfull
FFempty
Timeout
Bit 4
HRtag
Bit 3
HRdata
Bit 2
Stale
8-Bit Hex Address: 32
Default Value: 40
Bit 1
OneChar
Bit 0
DataErr
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Datasheet