CD1283 Datasheet, PDF (73/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
This register allows the peripheral host processor to issue special commands to the channel control
state-machine. In response, the state-machine will perform the indicated IEEE STD 1284-defined
handshake on the parallel interface.
Bit
7:5
4
3:2
1
0
7.4.12
Description
These read-only bits are always ‘0’.
TestMux: When this bit is set, the state of the state machine is multiplexed onto the GPIO pins for debugging
purposes.
GPIO is not possible when this bit is set.
Clear Pause and Set Pause: The Set and Clear Pause commands implement an error pause in Compatibility
mode. Usually, errors are presented to the host parallel port by the peripheral during the active BUSY period
of a data transfer. SetPs remains set until ClrPs is set, at which time both will clear.
In most cases, the slave host also sets RevRq at the same time when SetPs is set to:
1) lockup Compatibility mode with BUSY high, and
2) request a reverse transfer if the master requests that an additional status be sent in the reverse direction.
EPP Interrupt Request: This command causes the state machine to generate the EPP interrupt sequence.
The EPIrq bit clears on the initiation of the Intr (PerClk) pulse on the parallel port interface.
Reverse Request: This command requests that the host parallel port initiate the defined interface reversal
handshake as defined by the IEEE Std 1284 specification. The command bit clears to indicate completion
after the command has been executed on the interface. For Reverse Nibble and Reverse Byte modes, this
occurs after negotiation is complete; in ECP mode, it occurs after the Reverse Request signal on the parallel
port interface goes low.
In ECP mode, nPeriphRequest (nFault) is driven low to request that the host-side parallel port reverse the
direction of the interface.
When this bit is set upon termination to Compatibility mode, the CD1283 can indicate that reverse data is
available (through the nDataAv signal) immediately upon recognition of a Reverse-Nibble or Reverse-Byte
negotiation. To obtain this behavior, this bit should be initialized to ‘1’, and set to ‘1’ upon termination to
Compatibility mode.
Short Pulse Register
Register Name: SPR
Register Description: Short Pulse
Access: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
8-Bit Binary Value
Bit 2
8-Bit Hex Address: 26
Default Value: 00
Bit 1
Bit 0
This register performs two functions:
1. SPR sets the duration of the short pulse used by the IEEE 1284 protocols for all modes other
than Compatibility.
2. In Compatibility mode, SPR sets the duration of the ACK* pulse.
For Non-compatibility modes, SPR must be set to n − 2, where n is the number of CLKs in a 500-
ns pulse. The peripheral host initializes SPR with the appropriate value to generate a 500-ns pulse
width based on the operating frequency of the device.
In Compatibility mode, SPR should be set to the desired length of the ACK* pulse. This is
provided to enable the device to interface to slow masters that require an ACK* pulse longer than
the maximum specified in the IEEE 1284 specification. Table 11 shows examples of the necessary
binary value for various system clock frequencies to set the 500-ns pulse width.
Datasheet
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