CD1283 Datasheet, PDF (51/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
Figure 16. Polling Flow Chart
POLL DEVICE AGAIN
HARDWARE RESET
SOFTWARE RESET
INITIALIZE DEVICE
NOTE: It may not be necessary to poll the PFSR if
DMA requests are enabled. With DMA
requests enabled, the DMAREQ bit
(SVRR[7]) can be polled to determine when a
FIFO threshold is exceeded. If DMA requests
are disabled, the PFSR register must be
polled to determine when to move data to and
from the FIFO. If DMA requests are enabled,
data must be read through the DMABUF
register; this requires a 16-bit data bus.
POLL DEVICE AGAIN
DMAREQ
SET
SERVICE DMA REQUEST
CHANGE DIRECTION
RETURN ID TO HOST
DirCh
IDReq
nINIT
RESET PRINTER
TEST
SVRR
SRP SET
= _00H
TEST
PIR
Pipeline SET
PPort SET
TEST
PCISR
SigCh
TEST
SSR
NegCh SET
TEST
NSR
= 00H
TEST
PFSR
DataErr
FF FULL
OR
EMPTY
HR DATA
OR
HR TAG
TEST
HRSR
TEST
PFSR
SERVICE NEGOTIATION
CHANGE
SERVICE
SIGNAL
CHANGE
INTERRUPT
SERVICE
ERROR
INTERRUPT
SERVICE
APPROPRIATE
HOLDING
REGISTER
SVC.
FIFO
6.3
ASCII Code Tables
Table 8. Hexadecimal — Character (Sheet 1 of 2)
00 NUL 01 SOH 02 STX 03 ETX 04 EOT 05 ENQ 06 ACK 07 BEL
08 BS 09 HT 0A NL 0B VT 0C NP 0D CR 0E SO 0F SI
10 DLE 11 DC1 12 DC2 13 DC3 14 DC4 15 NAK 16 SYN 17 ETB
18 CAN 19 EM 1A SUB 1B ESC 1C FS 1D GS 1E RS 1F US
20 SP 21
!
22
“
23
#
24
$
25
%
26
&
27
‘
Datasheet
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