CD1283 Datasheet, PDF (17/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
Symbol
Pin No.
Type
Description (Sheet 2 of 3)
SVCREQP*
68
ACTIVE-LOW SERVICE REQUEST PARALLEL: This is an open-drain output and
must be tied to external V_CC through a pull-up resistor. Note that this output is only acti-
OD
vated by certain conditions on the parallel port (such as, negotiation changes, direction
changes, etc.). SVCREQP* is not activated by FIFO threshold, or FIFO full/empty con-
ditions (refer to Chapter 5.0 for information on how to use DMAREQ* to implement a
fully interrupt-driven system).
SVCACKP*
69
I
ACTIVE-LOW SERVICE ACKNOWLEDGE PARALLEL: This input must not be driven
active except in response to a parallel service request presented by the device.
DGRANT*
70
ACTIVE-LOW DAISY GRANT: This input is driven active during service acknowledge
I
cycles to enable the daisy-chain function. This input, when qualified with DS* and a
valid service acknowledge (SVCACKP*), activates the service acknowledge cycle.
DPASS*
ACTIVE-LOW DAISY PASS: This output is driven active during service acknowledge
cycles to enable the next device in the daisy-chain. It is driven active when no valid
71
O
service request exists and the service acknowledge input is active. In multiple CD1283
designs, this signal is normally connected to the DGRANT* input of the next device in
the chain.
PD[7:0]
41–48
PARALLEL PORT DATA LINES [7:0]: Bidirectional, depending on the protocol being
I/O used, these signals are used to transfer data over the interface between the master
and slave.
GP[7:0]
53–60
GENERAL-PURPOSE I/O [7:0]: General-purpose input/output port data lines. These
I/O
signals are individually direction-programmable, acting as inputs or outputs. The
direction of each signal is controlled by the corresponding bit in the GPDIR register.
Control/status of the actual signals is provided through the GPIO register.
A_1284
31
I
ACTIVE-HIGH 1284 ACTIVE INPUT: (SLCTIN* in Compatibility mode).
nInit
34
I
ACTIVE-LOW INIT SIGNAL: (INIT* in Compatibility mode).
HstBsy
32
I
ACTIVE-HIGH HOST BUSY SIGNAL: (AUTOFD* in Compatibility mode).
HstClk
33
I
ACTIVE-LOW HOST CLOCK SIGNAL: (STROBE* in Compatibility mode).
NOTE: The above four parallel handshake signals are driven by the master in an IEEE Std 1284 interface, and as such are
inputs to the CD1283. Their functions depend on the transfer protocol selected. Refer to the IEEE Std 1284-1994
document for protocol functions. (See Chapter 10.0 for ordering information.)
PerClk
37
O
ACTIVE-LOW PERIPHERAL CLOCK: (ACK* in Compatibility mode)
PerBsy
36
O
ACTIVE-HIGH PERIPHERAL BUSY: (BUSY in Compatibility mode)
AkDaRq
35
O
ACKNOWLEDGE DATA REQUEST: (PERROR* in Compatibility mode)
Xflag
39
O
EXTENSIBILITY FLAG: (SELECT in Compatibility mode)
nDatAv
38
O
ACTIVE-LOW DATA AVAILABLE SIGNAL: (FAULT* in Compatibility mode)
Datasheet
17