CD1283 Datasheet, PDF (84/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
Figure 24. Asynchronous DMA Write Cycle Timing
CLK
DMAACK*
DMAREQ*
DB[15:0]
t₁₉
MAY CHANGE
t₂₄
t₂₁
VALID
NOTE: This Figure 24 is still valid, however, Figure 25 illustrates a more robust timing.
Figure 25. Asynchronous DMA Write Cycle Timing
CLK
DMAACK* LATCHED
HERE
DMAACK* SYNCHRONIZED
HERE
DATA SAMPLED
HERE
DMAREQ*
DMAACK* SYNCHRONIZED
HERE
t₂₉
DATA SAMPLED
HERE
DMAACK*
t₂₈
t₃₀
t₃₀
SEE NOTE
DB[15:0]
t₃₂
t₃₁
t₃₂
t₃₁
VALID
VALID
NOTE: The data is sampled on the third rising edge of CLK following the assertion of DMAACK*. If DMAACK* is held
active for more than three CLK cycles then the next DMA write cycle will simply be delayed, but the data will
still be sampled on the third rising CLK edge following the assertion of DMAACK*. If DMAACK* is active for < 3
CLKs, the n the data is still sampled on the third rising CLK edge following the assertion of DMAACK*
(provided that DMAACK* is active long enough for the device to lastch it. Due to this somewhat synchronous
behavior, care must be taken to guarantee that the data is valid at this CLK edge. Do not assume that the data
will be sampled on the deassertion of DMAACK*.
8.3.2
Synchronous Timing
Use the following table as a reference to timing parameters of figures in this section.
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Datasheet