CD1283 Datasheet, PDF (62/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
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Bit
7:1
0
This register can be used to issue a hardware reset to the parallel channel
Description
These bits are not used and must always be ‘0’.
PChReset: When this bit is set, it asserts the equivalent of a hardware power-on reset to the parallel channel,
Channel 0. If set by the host, PChReset must be cleared to resume normal parallel channel operation. This hardware
reset affects only the parallel channel and has no effect on other functions of the device.
7.3.8
Parallel FIFO Control Register
Register Name: PFCR
Register Description: Parallel FIFO Control
Access: R/W
Bit 7
Bit 6
Bit 5
FIFOres
DMAen
DMAdir
Bit 4
IntEn
Bit 3
RLEen
Bit 2
setTAG
8-Bit Hex Address: 31
Default Value: 00
Bit 1
ErrEn
Bit 0
DMAbufWe
This register controls overall function of the parallel FIFO. These include resetting (flushing) the
FIFO, enabling DMA transfers, enabling host interrupts, run-length encoding, and so on. The host
sets these bits according to the mode of operation desired.
After hard reset (either through the RESET* input pin or by setting bit 0 in the PCRR), this register
is cleared to all zeroes.
Bit
Description (Sheet 1 of 2)
FIFO Reset: This bit must be set together with the correct value of DMAdir to properly initialize the data pipeline and
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FIFO registers for data transfer or when a new data transfer direction is desired. Data remaining in the FIFO is
discarded.
DMA Enable: This bit must be set for DMA requests to move data to/from the FIFO. When DMAen is set to ‘1’, the
PFQR quantity value is compared with the PFTR user-programmed threshold value. In Receive mode, if the
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threshold is equalled or exceeded, DMAREQ* is asserted to cause DMA data transfers of whole (2-byte) words from
the FIFO through the data pipeline. In Transmit mode, if the amount of data in the FIFO is equal or less than the
threshold, DMAREQ* is asserted to cause DMA data transfers of whole (2-byte) words to the FIFO through the data
pipeline.
DMA Direction: This bit sets the direction of transfer between the parallel FIFO and system memory. If DMAdir is set
to ‘1’, the direction is transmit (system memory to the parallel FIFO); if it is ‘0’ the direction is receive. The desired
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DMAdir value must be set together with FIFOres when initializing the FIFO logic for data transfer. Once a DMAdir
value is set and the FIFOres is complete, that DMAdir selection must be maintained during any other changes to the
control bits of the PFCR.
Interrupt Enable: This is the master interrupt enable for the parallel channel. This bit must be set for any interrupts
to be generated by the data pipeline, parallel port, or error status. In Poll-mode operation, host software may toggle
this bit to signal the completion of the service-acknowledge cycle and clear the current status in the PIR, SVRR, and
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LIVR. Toggling this bit updates the state of SVCREQP* and the PIR according to the current state of PCISR, DERR
and PFSR. For this reason, PCISR, DERR, and PFSR should be read and cleared at the beginning of the service
routine. These registers should be checked again at the end of the service routine to ensure that no requests were
skipped because an edge-sensitive interrupt controller may not detect a request that is already active when the
program returns from the service routine.
RLE Enable: This bit enables run-length encoding/decoding for direction defined by DMAdir. The RLEen bit affects
the flow of data through the data pipeline in the transmit direction. Data flow into the FIFO is managed in so that the
3
PFHR1 and PFHR2 are kept full to permit evaluation of data sequences for possible compression. The effect is that
following any data transfer while RLEen is set, the final 2 bytes written to the DMABUF register are kept in PFHR1
and PFHR2. To allow these bytes to be moved into the FIFO or to make room in PFHR1 for a tagged data transfer,
RLEen must be ‘0’ and both DMAen and DMAbufWe must be ‘0’.
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Datasheet