CD1283 Datasheet, PDF (27/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
As previously mentioned, the upper 5 bits of the LIVR reflect what the CPU loaded into them
during initialization of the CD1283s. These bits are used as a unique chip identification number.
Now the CPU can determine which CD1283 responded to the service acknowledge. These five bits
could be set to binary ‘0’ in the LIVRs of the first CD1283, and to binary ‘00001’ in those of the
second. The CPU is able to test the bits to determine which device responded. Some examples of
service-acknowledge software routines that show one way of performing this task are provided in
Chapter 6.0.
Caution:
If no CD1283 in the chain has a pending request, DGRANT* is passed by the last CD1283 and
none respond. This causes the bus cycle to fail (no DTACK* is generated). The only time this
happens is when an error condition outside the CD1283s cause the CPU to respond to a request
that is not made. Provide a mechanism to terminate or abort the bus cycle if this error occurs. This
can be accomplished with timeout circuitry, or the DPASS* output of the last CD1283 can
activate an abort condition. Other devices, such as the CD1400, can share the daisy-chain
mechanism and be connected to the DPASS* output of the last CD1283 in the chain. The actual
implementation is system-dependent, but it is important to provide some way for the CPU to
determine that the cycle did not complete normally if no device responds to the acknowledge cycle.
5.3
Parallel Port Service Requests
Service requests can derive from two internal sources: the data pipeline or the parallel port state
machine (Figure 5 on page 28). If the data pipeline internal service request becomes active, the
Pipeline bit (PIR[5]) is set; likewise, if the parallel port state machine internal service request
becomes active, the PPort bit (PIR[6]) is set. Internal service requests from these sources are
monitored through the Pipeline and PPort bits by microcode running in the internal MPU. When
either (or both) of these bits are detected active, the microcode sets the PPireq bit (PIR[7]). The
PPireq bit is also mirrored by the SRP bit (SVRR[3]). The SVRR is useful in polled systems
because it allows the detection of DMA service requests, as well as parallel port service requests
with a single register read operation.
Note: For specific register definitions and default settings, refer to Chapter 7.0.
Both internal sources of service requests within the parallel channel have their own enable
functions. Interrupts from the data pipeline are enabled through the PFCR; interrupts from the
parallel port state machine are enabled through the PCIER.
The PFCR has two enable bits: one for normal interrupts (such as tagged data being received), and
one for data errors (such as a CPU write to a holding register that already holds data). The first type
of interrupt is enabled through the IntEn bit (PFCR[4]). The second type of interrupt is enabled
through the ErrEn bit (PFCR[1]). Note that IntEn must be set for ErrEn to generate an interrupt;
however, the CPU need not enable error interrupts if it does not require notification of these types
of errors. The error interrupt is generated if the DataErr bit (PFSR[0]) is a non-zero. In this case,
the DER indicates the cause of the error interrupt.
The parallel channel-control state machine can generate six types of interrupts. Each of these has
its own enable bit in the PCIER:
• NegCh for negotiation changes
• SigCh for signal changes on the port status inputs (Manual mode only)
• EPPAW for EPP protocol address writes
• DirCh for direction changes on the parallel channel
Datasheet
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