CD1283 Datasheet, PDF (16/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
3.3
Pin Descriptions
Symbol
A[6:0]
Pin No.
84–90
BYTESWAP
82
CLK
73
CLK/2
80
CS*
78
DB[15:0]
92–99, 2–9
DS*
77
DTACK*
75
OUTEN
83
RESET*
79
R/W*
76
DMAREQ*
13
DMAACK*
12
Type
I
I
I
O
I
I/O
I
AR
I
I
I
O
I
Description (Sheet 1 of 3)
ADDRESS BUS: Together with CS* or one of the SVCACK* inputs and DS*, this input
selects an on-chip register for a read or write operation or an acknowledgment to a
service request.
BYTESWAP: This input determines the byte order for 2-byte DMA transfers and for
writes to the DMABUF register.
If BYTESWAP is set to ‘1’, Data Bus bits 15:8 are driven with the byte transferred first
on the parallel port bus. Data Bus bits 7:0 are driven with the byte transferred second
on the parallel port bus. If BYTESWAP is set to ‘0’, the data order is reversed, bits 7:0
are driven with the first byte transferred, and bits 15:8 are driven with the second byte
transferred.
SYSTEM CLOCK: This input has a 25 MHz maximum; 16 MHz is the recommended
minimum for satisfactory device performance.
SYSTEM CLOCK DIVIDED BY TWO OUTPUT: This signal is equivalent to the internal
operating clock of the device.
ACTIVE-LOW CHIP SELECT: When active, the input CS* in conjunction with DS*,
initiates a I/O cycle with the CD1283. CS* must be set to ‘1’ during DMA read/write
operations.
BIDIRECTIONAL DATA BUS [15:0]: Only DMA transfers and writes to the DMA Buffer
register are true 16-bit operations. During all register writes other than to the DMA
Buffer register, only bits 7:0 are written to the addressed register. Register reads
duplicate the register contents on both the lower byte, bits 7:0, and upper byte, bits
15:8.
ACTIVE-LOW DATA STROBE: During an active I/O cycle, the input DS* strobes data
into on-chip registers on write cycles or enables data onto the data bus during read
cycles. DS* is ignored during DMA operations.
ACTIVE-LOW DATA TRANSFER ACKNOWLEDGE: This output indicates: when the
device has completed the requested I/O operation, and when the cycle may finish. This
signal can be used to implement wait-state insertion for the local CPU. It is an Active
Release output, driving to logic ‘1’ then releasing to OD. DTACK* must be tied to
external V_CC with a pull-up resistor. DTACK* is not activated on DMA cycles.
OUTPUT ENABLE: This pin must be set to ‘1’ to enable output pin functions. When
OUTEN is set to ‘0’, it forces all pins that can act as outputs to remain in a tristate
condition.
OUTEN is used as a test input and is not normally used in an end application. User
designs should tie this pin to V_CC through a pull-up resistor.
ACTIVE-LOW RESET INPUT: Initializes the device to the default condition. All internal
registers are set to their reset condition and all transfer operations are set to the default
state.
READ/WRITE*: This pin must be set to ‘1’ for a register read operation and set to ‘0’
for a register write operation. This input is ignored for DMA operations.
ACTIVE-LOW DMA REQUEST: When the internal control bit DMAen is set, the output
DMAREQ* is asserted whenever internal FIFO conditions warrant a DMA transfer.
DMAREQ* is deasserted on the falling edge of DMAACK* when DMA transfers must
not continue past the current transfer.
ACTIVE-LOW DMA ACKNOWLEDGE: This signal must never be asserted unless in
response to a DMAREQ* from the device. DMAACK* is the only bus handshake signal
recognized during a DMA transfer. (CS* must be high whenever DMAACK* is
asserted.) The direction of the DMA transfer is determined by the internal control bit
DMAdir.
16
Datasheet