CD1283 Datasheet, PDF (14/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
3.2
14
Pin
Compati-
Names
bility
A_1284
HstBsy
HstClk
nInit
SLCTIN*
AUTOFD*
STROBE*
INIT*
AkDaR
q
PerBsy
PerClk
nDatAv
XFlag
PError
BUSY
ACK*
FAULT*
SELECT
Reverse
Nibble
Mode
Reverse
Byte ECP Mode
Mode
EPP
Mode
Inputs
A_1284
HstBsy
HstClk
nInit
A_1284
HstBsy
HstClk
nInit
Outputs
A_1284
HstAck
HstClk
nRevReq
nAStrb
nDStrb
nWrite
nInit
AkDaRq AkDaRq nAkRev USER1
PerBsy
PerClk
nDatAv
XFlag
PerBsy
PerClk
nDatAv
XFlag
PerAck
PerClk
nPerReq
XFlag
nWait
Intr
USER2
USER3
Pin List
The following naming conventions are used in the pin-assignment tables:
• (*) after a name indicates that the signal is active-low
• ‘I’ indicates the pin is input-only
• ‘O’ indicates the pin is output-only
• ‘I/O’ indicates the pin is bidirectional
• ‘OD’ indicates an open-drain output that the user must tie to V_CC through a pull-up resistor
(usually about 1 kΩ)
• ‘TS’ indicates tristate
• ‘PU’ indicates pull-up, which must also be tied to V_CC through a 1-kΩ resistor (note that all
six PU pins can be wire-OR’ed through the same pull-up resistor)
• ‘AR’ indicates active release (pin drives high and releases to OD)
• a ‘–’ indicates ascending pin numbers
• a ‘:’ indicates descending pin numbers
Pin Name
A[6:0]
BYTESWAP
CLK
CLK/2
CS*
Type
I
I
I
O
I
Number
of Pins
7
1
1
1
1
Pin
Numbers
84–90
82
73
80
78
Reset
State
n/a
Datasheet