CD1283 Datasheet, PDF (65/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
The PFSR is read-only and provides current FIFO and data pipeline status. Host software should
examine these bits in response to pipeline interrupts or for polling operations.
This register is not directly cleared by reset, but the individual bits will reflect the status of other
registers. This register is cleared by device or FIFO reset.
Bit
Description
7
Parallel FIFO Full: If this bit is set, it indicates the parallel FIFO is full.
6
Parallel FIFO Empty: If this bit is set, the parallel FIFO is empty.
Timeout: This bit is set when Stale goes from false to true. In the receive direction, Timeout is delayed until the FIFO
5
is empty and all DMA cycles are complete. Timeout is a pipeline-interrupt condition and must be cleared manually by
the CPU by toggling ClearTo in the PACR or by a FIFO reset in the PFCR.
Holding Register Tag: This bit indicates that a tagged character is in either the PFHR1, PFHR2, or both. This bit
4
being set will cause a host interrupt to be generated (if enabled). The host should examine the HRSR to determine
the exact cause(s) of this bit being set.
3
Holding Register Data: If this bit is set, it indicates that either the PFHR1, PFHR2, or both contain data.
Stale: This bit is set when the stale data timer expires (see description of SDTPR). If a single byte remains in the
2
data pipeline when this bit is set, a host interrupt is generated, the OneChar bit is set, and new data entering the
FIFO will not move into PFHR1 until PFHR2 is emptied. If two or more bytes remain in the pipeline when this bit is
set, a host interrupt is not generated, however, a DMA request will be generated if enabled.
One Character: In the receive direction, when this bit is set it indicates that the FIFO is empty and stale, and one
1
character remains in the PFHR2. This condition occurs if an odd number of bytes is transferred through the parallel
interface. Since DMA cycles only moves an even numbers of bytes (words), an odd transfer leaves one byte
remaining. Host software must remove this character outside of DMA transfer cycles.
0
Data Error: When this bit is set, it indicates that one or more of the bits in the DER (Data Error register) is set.
7.3.14
Parallel FIFO Threshold Register
Register Name: PFTR
Register Description: Parallel FIFO Threshold
Access: R/W
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
Bit 2
DMA Transfer Threshold
8-Bit Hex Address: 3B
Default Value: 00
Bit 1
Bit 0
This register sets the FIFO threshold for initiating DMA requests for data transfer. The value is
expressed in bytes. Whenever DMAen is true, regular comparisons are made between the PFQR
(Parallel FIFO Quantity register) and the PFTR. If the value in the PFQR is greater than or equal to
the threshold, the DMA request logic becomes active and remains active until the FIFO is
essentially filled or emptied. An odd character or space in the FIFO may remain.
In the receive direction, the Holding register pipeline (consisting of PFHR1 and PFHR2) and
DMABUF (if DMA is enabled) are kept filled so that tagged data (for example, ECP-mode
addresses) can be detected and passed to the host via an interrupt. If the FIFO and data pipeline are
initialized for receive and, for example, 40 hex bytes are placed into the FIFO from the parallel
port, the first two of those bytes is automatically placed in the Pipeline registers. If the PFTR were
programmed to x’40 bytes, x’44 bytes must arrive to trigger a DMA transfer.
PFTR is cleared by a device reset; it is not cleared by FIFOres.
Datasheet
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