CD1283 Datasheet, PDF (71/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
7.4.8
Parallel Channel Interrupt Enable Register
Register Name: PCIER
Register Description: Parallel Channel Interrupt Enable
Access: R/W
Bit 7
Bit 6
Bit 5
Bit 4
0
TimEn
NegCh
SigCh
Bit 3
EPPAW
Bit 2
DirCh
8-Bit Hex Address: 22
Default Value: 00
Bit 1
IDReq
Bit 0
nINIT
7.4.9
Parallel Channel Interrupt Status Register
Register Name: PCISR
Register Description: Parallel Channel Interrupt Status
Access: R/W
Bit 7
Bit 6
Bit 5
Bit 4
0
TimOvr
NegCh
SigCh
Bit 3
EPPAW
Bit 2
DirCh
8-Bit Hex Address: 23
Default Value: 00
Bit 1
IDReq
Bit 0
nINIT
The PCIER and PCISR provide control and status of interrupts generated by the parallel channel
control state machine. They have the same bit definitions. Each bit in the PCIER enables the
interrupt of the same type in the PCISR. A write of any value to the PCISR in response to an
interrupt request, causes it to clear and the interrupt request to be removed.
Bit
Description
7
Reserved: This read-only bit is always ‘0’.
6
TimEn/TimOvr: Used for factory test purposes only.
5
NegCh: The state of this bit indicates that a change occurred in the negotiation status of the port. The NSR
indicates the new status of the parallel port.
4
SigCh: This bit instructs the parallel port to generate an interrupt when any of the signals specified by the
ZDR or ODR change state as programmed.
3
EPPAW: The state of this bit indicates that the remote master has written an EPP address to the CD1283.
The new EPP address value is placed in the EAR.
DirCh: This bit indicates that the host-side parallel port changed the direction of the interface. Generally, this
2
is in response to a request made by the CD1283 through the RevRq bit in the SCR (bit 0). DirCh indicates that
the direction was reversed through the defined protocol and the CD1283 can now send data to the master.
This bit is only valid in ECP and EPP (bidirectional) modes.
1
IDReq: The state of this bit indicates that the host has requested that the CD1283 send its ID data string. The
peripheral host should send the appropriate ID string (this is application-dependent).
0
nINIT: This interrupt is generated when an nINIT pulse is received in Compatibility mode. The interrupt occurs
on the leading edge of the nINIT pulse.
7.4.10
Parallel Configuration Register
Register Name: PCR
Register Description: Parallel Configuration
Access: R/W
Bit 7
Bit 6
Bit 5
ManMd
E1284
ETxfr
Bit 4
Ig_SEL
Bit 3
HTmrTst[1]
Bit 2
HTmrTst[0]
8-Bit Hex Address: 20
Default Value: 00
Bit 1
MMDir
Bit 0
ManOE
Datasheet
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