CD1283 Datasheet, PDF (6/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
Figures
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Functional Block Diagram ................................................................................... 10
Functional Block Diagram ................................................................................... 23
Internal Address Generation ............................................................................... 23
CD1283 Daisy-Chain Configuration .................................................................... 26
Interrupt Generation Logic .................................................................................. 28
Control Signal Generation................................................................................... 31
FIFO Data Path Functional Diagram – Receive.................................................. 37
FIFO Data Path Functional Diagram: Transmit................................................... 38
Supported Compatibility Mode Timing ................................................................ 40
Cable Connection................................................................................................ 43
External Buffer Control........................................................................................ 44
Sample System Block Diagram........................................................................... 44
Intel‚ 80x86 Family Interface ............................................................................... 45
Motorola‚ 68020 Interface ................................................................................... 46
Flow Diagram of the CD1283 Master Initialization Sequence............................. 48
Polling Flow Chart ............................................................................................... 51
Reset Timing ....................................................................................................... 79
Clock Timing ....................................................................................................... 80
Asynchronous Read Cycle Timing ...................................................................... 80
Asynchronous Write Cycle Timing ...................................................................... 81
Asynchronous Service Acknowledge Cycle Timing ............................................ 82
Asynchronous DMA Read Cycle Timing ............................................................. 83
Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads) ........ 83
Asynchronous DMA Write Cycle Timing ............................................................. 84
Asynchronous DMA Write Cycle Timing ............................................................. 84
Synchronous Read Cycle Timing........................................................................ 86
Synchronous Write Cycle Timing ........................................................................ 87
Synchronous Service Acknowledge Cycle Timing .............................................. 88
Synchronous DMA Write Cycle Timing
(Two Back-to-Back 3-Cycle DMA Writes) ........................................................... 89
Synchronous DMA Read Cycle Timing
(Two Back-to-Back 3-Cycle DMA Reads) ........................................................... 89
Tables
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Global Registers.................................................................................................. 19
Virtual Registers.................................................................................................. 20
Parallel Pipeline Registers .................................................................................. 20
Parallel Port Registers ........................................................................................ 20
Special Register .................................................................................................. 21
LIVR[2:0] Encoding ............................................................................................. 31
System Clock Setup............................................................................................ 42
Hexadecimal — Character .................................................................................. 51
Decimal — Character.......................................................................................... 52
PIVR[2:0] Encoding............................................................................................. 56
SPR Binary Values to Set 500-ns Pulse Widths ................................................. 74
Asynchronous Timing Reference Parameters .................................................... 78
Synchronous Timing Reference Parameters ...................................................... 85
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Datasheet