CD1283 Datasheet, PDF (32/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
5.3.1
5.3.2
5.4
Hardware-Activated Acknowledge
When conditions within the parallel channel require attention, a request is made through the
SVCREQP* output. If the system is interrupt driven, this output is connected to the CPU interrupt-
generation circuitry. In a hardware-activated service-acknowledge system, the CPU responds to the
request by activating the SVCACKP* input along with DGRANT* and DS*; the CS* input is not
used and must remain inactive (high). The CD1283 responds to the SVCACKP* cycle by driving
the contents of the PIVR onto the data bus with IT2–IT0 encoded as shown in Table 6. The
SVCACKP* cycle also places the device in the correct context to service the parallel channel
request.
The vector supplied by the PIVR indicates which block of the parallel channel requested service;
the cause of the request is indicated in the status request registers of each; the PCISR in the channel
control state machine block and/or the PFSR in the data pipeline block.
The I/O cycle that activates the SVCACKP* input also removes the active SVCREQP* output. The
request output remains inactive until after the CPU terminates the acknowledge routine by a write
to the EOSRR. This is a dummy operation and the data written is ‘don’t care’. The purpose of the
write is to clear the internal logic of the current request context and allow it to generate another
request when required. Until this write occurs, no further service requests can be made from the
parallel channel. When the MPU detects the write to the EOSRR, it clears the PIVR bits to ‘0’ in
preparation for the next service-request cycle.
Software-Activated Acknowledge
During a normal read cycle, the LIVR always reads back with the lower 3 bits, indicating the
current service-request status of the device. Thus, in a Poll-mode system, this register can be used
in conjunction with the SVRR to determine if service request needs are pending and, if so, which of
the two possible sources is active. If the SRP bit is set (SVRR[3]), at least one of the request
conditions is true and a subsequent read of the LIVR indicates the source. A scan of just the SVRR
allows the polling routine to perform only one read cycle to determine if a parallel request is
pending. If the SVRR indicates an active parallel channel service request, the software can initiate
the appropriate service routine that reads PIR to determine the source of the parallel port request.
The PPort and Pipeline bits indicate the block requesting service.
Once the CPU satisfies the request needs of the parallel channel, it must toggle the IntEn bit
(PFCR[4]) or clear the PIR. Toggling IntEn clears the PPireq, PPort, and Pipeline bits (PIR[7:5]).
This action also informs the MPU to clear the PIVR and remove the external request.
The PPireq bit can be cleared at any time by the CPU once it enters the service routine. If the
system design requires that the request be removed quickly, this procedure can be performed at the
beginning of the polled service routine. After the interrupt source is determined, the CPU can clear
PIR or toggle IntEn, then the PIR is automatically cleared.
Parallel Port FIFO and Data Pipeline
The parallel port within the CD1283 implements all modes defined for the ‘slave’ (peripheral) side
of the IEEE STD 1284 Standard Signaling Method for a Bidirectional Parallel Peripheral
Interface for Personal Computers. This specification defines four methods of performing
bidirectional data transfers between a computer system and a peripheral device, in addition to the
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