CD1283 Datasheet, PDF (26/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
Section 5.2.4). However, the software can easily change this by clearing the DMAen bit
(PFCR[6]) at the start of the interrupt service routine and setting it again at the end.
4. If SVCREQP* and DMAREQ* are logically OR’ed together, the service routine must start by
checking the SVRR to determine which signal is active.
5. SVCACKP* must not be activated in response to DMAREQ*; likewise, DMAACK* must not
be activated in response to SVCREQ*.
6. The DMAdir bit (PFCR[5]) can determine whether to write or read to/from the DMABUF
register.
7. The PFQR can determine how many reads of the 16-bit DMABUF register are necessary to
empty the pipeline. Note however, four must be added to the PFQR value, then that number
then must be divided by two and truncated to the nearest integer (this accounts for the extra
four bytes in the two holding registers and the 16-bit DMABUF register, as well as 16-bit
instead of 8-bit reads).
5.2.7
Daisy-Chain Configurations
Multiple CD1283s can be connected in a daisy-chain configuration, forming systems with multiple
parallel ports. The device provides all signals necessary for this configuration, with only minimal
external logic being (Figure 4).
When the CPU acknowledges the request, both CD1283s receive the acknowledge through
SVCACK*. However, only the device receives DGRANT*. If it has an active request of this type
pending, it takes the acknowledge and drives the vector register (RIVR, TIVR, MIVR) onto the
data bus.
If the first device does not have a request pending, it passes DGRANT* to the second CD1283
through DPASS*. Assuming that the second CD1283 has an active request pending, it then takes
the acknowledge and drives its vector register onto the data bus.
Figure 4. CD1283 Daisy-Chain Configuration
ADDRESS
DECODE
LOGIC
SVCACKP*
DPASS*
DGRANT*
SVCREQP*
CD1283
SVCACKP*
DGRANT*
DPASS*
SVCREQP*
CD1283
CYCLE
ERROR
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Datasheet