CD1283 Datasheet, PDF (33/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
generally accepted unidirectional Centronics^-compatible mode. These modes include
Compatibility mode, Reverse-Nibble mode, Reverse-Byte mode, ECP (Extended Capabilities port)
with and without RLE (run-length encoding, and the EPP (Enhanced Parallel port).
The IEEE 1284-compliant parallel port consists of two major functional blocks:
• A data pipeline that moves data between the parallel port and the CPU and includes a FIFO,
holding registers, DMA control, and interrupt control logic.
• A channel control state machine to performs all control and handshake generation on the
parallel port interface side of the device.
5.4.1
IEEE Standard 1284 Protocols
The following sections discuss data movement within the pipeline for the various IEEE Std 1284
operating modes. For a complete description of these modes, refer to the IEEE Std 1284
specification; it is beyond the scope of this data book to relate complete information on the
specification. A copy of the IEEE Std 1284-1994 can be obtained from:
IEEE Standards Department
445 Hoes Lane
P.O. Box 1331
Piscataway, NJ 08855-1331
USA
5.4.2
Bus Interface
DMA transfers are the preferred means of transferring data to/from the FIFO. However, it is also
possible to transfer data to/from the data pipeline by reading and writing the holding registers
directly through PIO. DMA request and acknowledge handshake signals support transfers to/from
the 16-bit-wide DMABUF register. The direction of transfer is determined by the DMAdir bit
(PFCR[5]).
In the transmit direction, with DMAbufWe set (PFCR[0]), the CPU can write 2 bytes at a time
directly to the DMABUF register. However, most applications are not concerned with speed on the
parallel port in the reverse direction and do not require 16-bit writes to the FIFO. The CPU must
avoid writing to these registers when they are already full or reading from them if they are empty.
The status bits in the HRSR indicate if the holding registers and the DMA buffer are full or empty.
When writing a block of data to the CD1283 (with DMAbufWe set to ‘1’), the CPU can determine
how much data the FIFO can accommodate by reading the PFQR.
Should data become ‘trapped’ in the DMABUF register in the receive direction because of a failure
of the external DMA controller or because the external buffer area is full, it can either remain until
the DMA transfer can be resumed or the CPU can read the data directly from the DMA buffer.
Note: The DMA buffer can only be read when DMAREQ* is active because data is not moved into the
DMABUF register until DMAREQ* is activated by the threshold logic or a timeout condition.
Once a DMA request is initiated by the CD1283, it is maintained until the last data transfer the
FIFO can accommodate occurs, or the CPU either clears DMAen or clears the FIFO and data-
transfer logic by setting FIFOres. In the transmit direction, the DMA request is removed by the
CD1283 when it determines that the FIFO is nearly full. (If RLEen is set, the pipeline does not
fully drain into the FIFO, but the logic does not factor that into the decision to conclude the DMA
transfer.)
Datasheet
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