CD1283 Datasheet, PDF (58/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
7.3.2
DMA Buffer Data Register
Register Name: DMABUF
Register Description: DMA Buffer Data high
Access: R/W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
DMA Buffer Data High Byte
Bit 10
8-Bit Hex Address: 30
Default Value: 00
Bit 9
Bit 8
Register Name: DMABUF
Register Description: DMA Buffer Data low
Access: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DMA Buffer Data Low Byte
Bit 2
8-Bit Hex Address: 30
Default Value: 00
Bit 1
Bit 0
This 16-bit data register is used to buffer DMA data transfers to and from the CD1283. Under
normal operating conditions, this register is only accessed during a DMA data transfer cycle. If
DMAbufWe (PFCR0) is set to ‘1’ and DMAdir (PFCR[5]) is set to ‘1’, 16-bit data can be
transferred from the host to the FIFO by directly writing to the DMABUF. The data automatically
moves forward into the FIFO through the Data Pipeline Holding registers. The user must ensure
that the FIFO has sufficient free space to accept the data before writing into the DMABUF.
The BYTESWAP pin determines the order of byte transfer from this register into the data pipeline.
If BYTESWAP is set to ‘1’, data transferred on DB[15:8] is the first byte transferred into the data
pipeline and DB[7:0] is transferred second. If BYTESWAP is set to ‘0’ this sequence is reversed.
The same applies during data read during DMA transfers: if BYTESWAP is set to ‘1’, data from
the data pipeline moves to the upper byte of DMABUF, the next byte moves into the lower byte.
Again, if BYTESWAP is set to ‘0’, this sequence is reversed.
These resisters can be read through DMA acknowledge or PIO cycles. However, the DMABUF
registers can only be read when the DMAREQ* signal is active. If DMAREQ* is inactive, the
DMABUF registers will be empty. DMAfull (HRSR[3]) indicates if the DMABUF register is
empty when DMAREQ* is inactive.
7.3.3
Holding Register Status Register
Register Name: HRSR
Register Description: Holding Status
Access: Read only
Bit 7
Bit 6
Bit 5
HR1full
HR1tag
HR2full
Bit 4
HR2tag
Bit 3
DMAfull
Bit 2
DMAmpty
8-Bit Hex Address: 34
Default Value: 04
Bit 1
DMAact
Bit 0
Ctnot0
The HRSR is read-only and indicates current data pipeline status This register is not directly set to
any particular value at device reset, but reflects the current state of bits in other registers
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Datasheet