CD1283 Datasheet, PDF (41/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
5.6.3
5.6.4
5.6.5
5.7
There is no mechanism in Compatibility mode for the slave to indicate that data is available for
reverse transfers. The master must poll the slave by negotiating into a reverse mode and examining
the nDatAv signal. The RevRq (SCR[0]) instructs the CD1283 to post the availability of data to the
master through the nDatAv signal.
ID Request
ID request is enabled with a combination of NER[6] and one of four other transfer mode bits. ID
requests can be made in conjunction with ECP, ECP/RLE, Reverse-Byte, and Reverse-Nibble
modes; there is no ID request function defined for EPP mode. The CD1283 can accept an ID
request in any mode enabled to manage transfers. IDReq is set when an ID request is received in
any enabled mode.
ECP Mode
ECP mode allows bidirectional transfers and supports the RLE-compression scheme. The ability to
expand RLE data is required of all IEEE-1284, ECP-compliant devices, but the ability to compress
data is optional. The CD1283 handles both expansion and compression in the data path section.
The parallel port simply passes the inverse of the command signal to/from the FIFO on the ninth
tag bit in the FIFO. ECP mode is enabled by NER[2]. RLE mode enabling requires both NER bits
2 and 3.
The handshake is identical for both ECP and RLE modes. The control signals, HstBsy and PerBsy
(in the forward and reverse directions, respectively), indicate command and address options. If
HstBsy/PerBsy is low, the upper bit of the byte is examined: ‘0’ indicates to interpret the lower 7
bits as an address; ‘1’ indicates to use the lower 7 bits as an RLE repeat count. This count shows
the number of times to consecutively repeat that the next data character in the datastream.
The master device is responsible for determining the direction of the transfer. The slave can request
a direction change, but the master actually changes the direction. ECP mode always begins in the
forward direction, from master to slave. The CPU sets the RevRq bit (SCR[0]) to request reverse
transfers. Once the master changes direction, RevRq is automatically cleared and the DirCh
interrupt status appears in PCISR (if enabled in the PCIER).
The master device switches the direction of the interface for forward transfers when the slave
indicates no more data is available.
EPP Mode
Data transfers use the DMA pipeline and the FIFO. Address transfers are handled out-of-band, not
in the FIFO stream. When the slave receives an address write command, it deposits the address into
the EAR and asserts an EPPAW interrupt request. When the slave receives a read address
command, the contents of the EAR are returned.
Protocol Timing
The IEEE-1284 specification timing parameter, T_P, specifies the minimum pulse width and the
minimum setup time as 500 ns. The SPR must be loaded with the number of system clock ticks
equivalent to 500 ns, as shown in Table 7.
Datasheet
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