CD1283 Datasheet, PDF (36/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
‘0’. When Stale becomes ‘1’, the timeout is triggered, but not set until any DMA transfer is
complete, the FIFO is empty, and there is no more than one character left in the pipeline. To clear
the timeout condition, set the ClrTO bit. To reenable the timeout function, clear ClrTO.
The CPU can arm the timeout by a write of ‘01h’ directly to the SDTCR. If the timer expires before
any data arrives, an interrupt is generated for the timeout condition. If data arrives before the timer
expires, the interrupt delays until the data becomes stale.
5.4.7
Transmit Direction
Note:
In the transmit direction, the pipeline behaves in one of two ways depending on the state of the
RLEen control bit. RLEen should only be set by the CPU after the parallel port is in ECP mode,
otherwise compression of data occurs, but cannot be supported in data transfers on the parallel port.
If RLEen is ‘0,’ data written to the DMABUF register by a DMA (DMAen true) or CPU write
(DMAbufWe true) will be moved through PFHR1 to PFHR2 and immediately transferred into the
FIFO (if space is available).
If RLEen is ‘1,’ run-length encoding is enabled and comparators among the pipeline stages
recognize repeated strings of characters and compress them (Figure 8 on page 38). To allow the
comparator-based logic to work, the pipeline registers, PFHR1 and PFHR2, must be kept full. One
comparator determines if the characters in PFHR1 and PFHR2 are identical.
Another comparator determines if the next character coming from the DMABUF register and the
character in PFHR1 are identical. Compression begins when the pipeline is full (immediately after
a DMA or CPU write to the DMA buffer) and both comparators show identical characters in their
pipeline stages. This starts the compression process and the character in PFHR1 and the character
in the DMA buffer are shifted forward. The (same) character in PFHR2 is not loaded into the FIFO,
but rather the RLCR is increments to ‘1.’ As long as identical additional characters are loaded into
the DMA buffer, the RLCR value continues to increment and the data in PFHR2 is not moved into
the FIFO. When the repeated sequence is finally broken or the RLCR count reaches 127, the RLCR
value transfers into the FIFO, the RLCR zeroes, and the character in PFHR2 transfers into the
FIFO. Compression resumes when both comparators again indicate the presence of a string of at
least three identical characters. During intervals between DMA transfers, the last two data
characters are held in PFHR1 and PFHR2.
After the entire block transfer is complete, the CPU must either force RLEen to ‘0’ or ensure that
both DMAen and DMAbufWe are ‘0’. When either of these conditions is true, the pipeline is
released and the data held in PFHR1 and PFHR2 transfers into the FIFO.
The timeout interrupt can be used as a general timer interrupt in the transmit direction. Unlike the
receive scenario, when DMAdir is true, the Timeout status bit is immediately set when the timeout
is triggered by a ‘0’-to-‘1’ transition of Stale. To use the timeout interrupt, the CPU must load the
desired time delay directly into the SDTCR. When the timer expires, Stale becomes true and the
timeout interrupt is activated.
5.5
5.5.1
Parallel Port Overview
Terminology
This document uses the terms ‘master’ and ‘slave’ for the IEEE-1284-specification terms ‘host’
and ‘peripheral’, which describe the two sides of a parallel port interface.
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Datasheet