CD1283 Datasheet, PDF (29/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
Figure 5. Interrupt Generation Logic (Continued)
A1284 signal transition nInit signal transition
from low-to-high, and from low-to-high, and
A1284(ODR[3]) = 1
nInit(ODR[2]) = 1
HstBsy signal transition HstClk signal transition
from low-to-high, and from low-to-high, and
HstBsy(ODR[1]) = 1
HstClk(ODR[0]) = 1
NOTE: Interface must be in Compatibility mode when
ManMd (PCR[7]) is set or ManMd has no affect
A1284 signal transi-
tion from high-to-low,
and
A1284(ZDR[3]) = 1
nInit signal transition
from high to low, and
nInit(ZDR[2]) = 1
HstBsy signal transi-
tion from high-to-low,
and
HstBsy(ZDR[1]) = 1
Host has reversed the direction of the interface from ECP-forward to
ECP-reverse by driving nReverseRequest (nInit) signal low.
HstClk signal transition
from high-to-low, and
HstClk(ZDR[0]) = 1
ManMd
(PCR[7])
SigCh
(PCIER[4])
EPP address received
on parallel port
EPPAW
(PCIER[3])
SigCh
(PCISR[4])
EPPAW
(PCISR[3])
DirCh
(PCISR[2])
Host has changed the direction of the interface from ECP-reverse to ECP-
forward by driving nReverseRequest (nInit) signal high.
In Compatibility mode, the host
has requested the peripheral to
re-initialize itself (nInit went
low).
(PCISR[5]) (PCISR[4]) (PCISR[3]) (PCISR[2])
NegCh
SigCh
EPPAW
DirCh
(PCISR[1])
IDReq
(PCISR[0])
nInit
nInit
(PCIER[0])
INTEN
(PFCR[4])
nInit
(PCISR[0])
PPort
(PIR[6])
Datasheet
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