CD1283 Datasheet, PDF (59/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

IEEE 1284-Compatible Parallel Interface — CD1283
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Bit
7:6
5:4
3:2
1
0
Description
HR1full and HR1tag:These two bits indicate status of PFHR1. Bit 7 indicates that the register contains data and
bit 6 indicates that the data is tagged. Both bits can be set simultaneously.
HR2full and HR2tag:These two bits indicate status of PFHR2. Bit 5 indicates that the register contains data and
bit 4 indicates that the data is tagged. Both bits can be set simultaneously.
DMAfull and DMAmpty: These two bits indicate status of the DMA transfer buffer (DMA buffer). Bit 3 indicates
that the register contains data and bit 2 indicates that it is empty.
DMAact: This bit when set, indicates that the DMA handshake is active and that DMA service is requested, but
not yet complete (DMAREQ* active, waiting for DMAACK*).
Ctnot0: This bit indicates that the RLE counter is not zero, thus run-length encoding/decoding is in progress.
7.3.4
Host Timeout Value Register
Register Name: HTVR
Register Description: Host Timeout Value
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Host Timeout Period
Bit 2
8-Bit Hex Address: 24
Default Value: FF
Bit 1
Bit 0
HVTR holds the 8-bit value used to set the Host Timeout period. The HTVR is an unsigned, binary
value. The reset state of this register is ‘0xFF’.
A function missing in the revision ‘C’ and earlier devices is an on-chip timer to indicate that the
remote host has not responded in a specified time period. The Host timeout is defined in the IEEE
STD 1284 Specification as a period of one second.
The revision ‘D’ device adds a user-programmable timer that provides a timeout if the remote host
does not respond to specific parallel port transactions. The timer is started by the parallel port state
machine each time it starts a sequence requiring a host response. Activation of the timer is
automatic and an interrupt is generated to the local host CPU if the timer expires before the remote
host responds.
Note:
Users familiar with the IEEE specification note that the events that start the timer cause the
peripheral device to move to a state where it waits for a remote host-generated event. For example,
during the negotiation sequence after event 2, the peripheral waits for event 3, a host-generated
event. If the host does not respond and moves the negotiation sequence to event 4 within one
second, the peripheral enters the ‘host Timeout’ condition.
The timer is a 14-bit counter clocked by the system clock (CLK) prescaled (divided) by 2048.
Program the 8-bit Host timeout Value register (HTVR, address offset 0x’24), which is then
compared with the most-significant 8 bits of the 14-bit counter. Each time the parallel port executes
an event requiring a host response, the 14-bit counter is started (from 0x’00). It counts up until
either the expected event occurs or the count matches the value in HTVR. If a match occurs, a
timeout condition exists. The HTVR need only be loaded once, typically during device
initialization.
The value placed in HTVR yields an approximate one second count time, based on the value of the
input CLK. For example, if the system clock driving the device is 25 MHz, the HTVR should be
loaded with 0xC0. The following equation provides an example.
Datasheet
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