CD1283 Datasheet, PDF (1/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283
IEEE 1284-Compatible Parallel Interface
Product Features
Datasheet
Parallel Port (Peripheral-side)
High-speed, bidirectional, multi-protocol
parallel port:
s Hardware implementation of all modes of
the IEEE STD (Standard) 1284
specification (including automatic
negotiation)
— Centronics^-compatible mode
— Reverse Byte mode
— Reverse Nibble mode
— ECP (extended capabilities port) mode
with run-length encoding/decoding
— EPP (enhanced parallel port) mode
— Up to 2-Mbytes/sec. transfer rate in ECP
and EPP modes
s 64-byte parallel FIFO with DMA interface
— 64-byte FIFO can accommodate up to 4
Kbytes of compressed data with RLE
(run-length encoded) compression
enabled
s Supports peripheral-side operation
s Data and control input/output pads support
IEEE STD1284 level-2 interface
specification
s CPU bus interface
— High-speed slave DMA handshake
interface
— Three clocks per word DMA transfers
— On-the-fly data compression using RLE
(run-length encoded) encoding and
decoding
s 8/16-bit data interface
— BYTESWAP input provides easy
interface to both Big- and Little-Endian
systems
— Vectored interrupts simplify interrupt
service routines
General
s System clock up to 25 MHz
s CMOS technology enables high speed and
low power
s Available in a 100-pin MQFP package
As of May 2001, this document replaces the Basis
Communications Corp. document CL-CD1283 — IEEE 1284-Compatible Parallel Interface.
May 2001