CD1283 Datasheet, PDF (24/94 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface

CD1283 — IEEE 1284-Compatible Parallel Interface
5.2.1
Read Cycles
Read cycles are initiated when both the CS* and DS* inputs are activated and the R/W* (read/
write) input is high. All strobes and address inputs must meet the setup times as specified in
Chapter 8.0. Both the CS* and DS* signals must be valid for a cycle to start. Cycle times are
measured from whichever of the two signals goes active last. The CD1283 signals the completion
of the read cycle (placing the data from the addressed register on the data bus pins) by activating
DTACK*. The read cycle terminates when the CPU removes CS* and DS*.
5.2.2
Write Cycles
Write cycle timing and strobe activity is nearly identical to read cycles except that the R/W* signal
must be held low. Write data, strobes, and address inputs must meet setup and hold times as
specified in Chapter 8.0. DTACK* indicates that the cycle is complete and the CD1283 has
accepted the data. Removing both CS* and DS* terminates the cycle.
5.2.3
Service-Acknowledge Cycles
Service-acknowledge cycles are a special-case read cycle. Timing is basically the same as a normal
read cycle, but the SVCACKP* input is activated instead of the CS* input (a slightly longer setup
time is required on the SVCACKP* input than on the CS* input). The data that the CD1283
provides during the read cycle is the contents of the PIVR. As with read and write cycles,
DTACK* indicates the end of the cycle and removing DS* and SVCACK* terminates the cycle.
Note:
With regard to timing and service-acknowledge cycles, when the CPU completes the service
routine and writes to the EOSRR, a subsequent I/O cycle, if started immediately, is delayed
approximately 1 µs by delaying DTACK*. This is due to the time required by the internal processor
to complete activities associated with the service-acknowledge cycle.
These activities are primarily interrupt-logic updates and restoration of the environment prior to the
service-request/service-acknowledge procedure. These must be completed before any internal
registers are modified by the CPU.
If the CPU attempts an access before the internal procedures are complete, the CD1283 will hold
off the cycle until it is ready. In system designs that monitor DTACK*, this is not a problem; the
cycle is extended until DTACK* becomes active, and the delay is automatically met. If a system
design does not monitor DTACK*, a mechanism must be provided to introduce the required delay.
Warning: Failure to observe the above delay requirement can cause device malfunction.
5.2.4
DMA Cycles
The CD1283 provides a bidirectional, 16-bit DMA interface to the parallel port. This is the only
direct-data interface to the port; other 8-bit register accesses make use of the normal CPU interface,
as previously described.
The handshake between the CD1283 and the DMA circuitry uses two signals: DMAREQ* and
DMAACK*. The address bus is ignored during DMA transfers. When internal conditions warrant
a DMA transfer (as when the FIFO falls below the programmed threshold in the forward direction
or rises above the threshold in the reverse direction) and DMA transfers are enabled through the
PFCR, the device requests DMA service by driving DMAREQ* low. DMAREQ* remains active
until the FIFO has less than two empty byte locations remaining (forward direction) or until the
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Datasheet