81348 Datasheet, PDF (76/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Electrical Specifications
Table 29.
PCI Express* Tx Output Specifications
Symbol
Parameter
Min. Nom Max Units Notes
UI
Unit Interval
400
ps 1
V_DIFFp-p
Differential output voltage
0.800
1.200 V 2
T_rise, T_fall
Driver Rise/Fall Time
0.2
0.4 UI 3
V_TX-CM-AC
AC Common Mode
20 mV 4
V_{TX-CM-DC delta} Common Mode Active to Sleep mode delta -50
+50 mV
RL-Diff_TX
Differential Return Loss
15
dB 5
RL-CM_TX
Common Mode Return Loss
6
dB 5
Z_TX-OUT-DC DC Differential Output Impedance
90 100 110 Ω 6
Z_TX-Match-DC D+/D- impedance matching
-5
+5 % 7
L_SKEW-TX
Lane to Lane Skew at Tx
500 ps 8
J_TOTAL
Total Output Jitter.
0.35 UI 9
T_Deye
Minimum Transmitter eye opening.
0.65
UI 10
I_TX-SHORT
Short circuit Current
-100
100 mA 11
V_TX-IDLE
Sleep mode Voltage Output
0
0 20 mV 12
Notes:
1. ±300 ppm. UI does not account for SSC dictated variations. No test load is necessarily associated
with this value. This UI specification is a “before transmission” specification and represents the
nominal time of each bit transmission or width.
2.
Pmloeaaadxki-maPseuasmhkosdwiinfnfgelierneenFntigidauelrdveov2lot2alt,ga“egT.eraVan_{DfsItFmeFrpit-atper=reTf2leesc×ttiLoVonDaMfdrAox(m.1S0pa0neΩ}coifpdieeifdnf _{.aLTot ahthdise)”vpaoalnucekpaaigsgeefop8ri3nth.seMinfatixrosltaebv1iet0l0asfe}Ω_{tet rtbeayst}
transition on the data lines. Subsequent bits of the same polarity shall have an amplitude of 6 dB
(±0.5 db) less as measured differentially peak to peak than the specified value.
3. 20–80% at transmitter. Slower rise/fall times are better.
4.
5.
Peak common
50 MHz to 1.6
mGHodz.eTvhaeluder.iv|eVr_{Do+u+tpVutD-im|/2pe-dVaCnMce-DsCh(aavlgl )result}
in
a
differential
return
loss
greater
than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The
rtAcheopifmpselrmiiecsnaobbcnaelesmeimdodudporeeinnd(gaai.neanc.coetamivsfoienmra(reLlea0Pts)uCuraIrnneEddlxopsAbrsyleigmsanse*VsaetisancutttoreeersrmcNooeennntlnywte.socirtskd1Aif0nf0earlΩ_{eynzfetoirar lwdciifhtfhaerr1ae0cn0tteiaΩrilsrdteiicftfueimrrnepnleotdisaaslnapcnreodbo2ef} 5s1)0.Ω_0NfoΩotr.e
6. _{iDmCpDedifafenrceenmtiaaltcMhoindge cImircpueitdsatnoceen1s0u0re}Ω_{th±e10b%esttoploesrsainbclee.teArlml} dineavticioens/sZhoaultl _feomr pitlsoyTroann-scmhiiptteardsa(patsivweell
as receivers).
7. DC impedance matching between two lanes of a port.
8. Between any two lanes within a single transmitter.
91.0. _{SCeloeckFisgouurerc2e3P,P“MTrmanissmmiatttcehr EisyienDaidadgirtaiomn”toonthpiasgveal8u4e..} Measured over 250 UI.
11. Between any voltage from max supply to gnd with power on or off.
12. Squelch condition. Both signals brought to V_{CM-DC-|VD+ - VD-|}
DInatteal^®sh8e1et348 ^{I/O Processor}
76
December 2007
Order Number: 315038-003US