81348 Datasheet, PDF (29/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Package Information—Intel^® 81348
Table 10.
UART Signals (Sheet 1 of 2)
Name
Count Type
Description
U0_RXD
U0_TXD
1
I UART 0 Serial Input: Serial data input from device pin to the receive
Async ^{shift register.}
1
O
Async
UcoAmRTm0unSicearitaiolnOsultipnuk-t:peCroipmhpeorasli,temsoedreiaml d, aotradoautatpsuettt.oThtheeTXD
signal is set to the MARKING (logic 1) state upon a reset operation.
U0_CTS#
U0_RTS#
I
ActLow
Async
CTS# ^{UART 0 Clear to Send: When low, this pin indicates that the receiving UART}
is ready to receive data. When the receiving UART deasserts
high, the
CTS# ^{transmitting UART must stop transmission to prevent overflow of the}
receiving UART buffer. The
signal is a modem-status input whose
condition can be tested by the host processor or by the UART when in
Autoflow Mode as described below:
Non-Autoflow Mode:
When not in ARiusettgohfiselotewcor _{mM(MopdSleeRm,)beinnitdt[4ioc]af t(teChsTeStCh)TeoSsf#ttahsteeigMonfaoCld.eTBmSit#[S.0t]Baittu[4s]}
(wthDheCeTpthSree)vroitofhutesheCreTMaSod#dineignmpouSftttahhteaussMcoRhdeaegnmigsteeSdrtasinttaudtsiecastiensce
1
RTprheogeciseutssesero.rrCcwaTnShe#pnrhoDagCsraTnmSo _{ctehhfefaenUcgtAeoRsnTsttthaoteeint.rtaTehnrresumpittttehre.}
Note:
psthtrreoegaUrmaAmRbTmywesrittahcravtnhinetghIetEhnResrtteragallniststhmeer.itouFItgFOoinogr _{ddiastaabling}
WtrhehaeseusnseeUrtrAsd.RoTTehtsirsanniosstmbreeisccsaeiuiovsneeiasdnisstaMabSllleiRndginbttyheerdriUuspaAtbRlwTinhagelsntohCedTiUsSAa#bRlTe,s
iinntAerurtuopfltosw. TMoowdoer,koarrporuongdratmhist,hteheCTuSs#er _{pcianntousientAeurrtuopCt.TS}
AutoInfloAwutMofolodwe:Mode, _{the UART transmit circuity checks the state of}
CisThSi#ghb,enfoordeattraanissmtraitntisnmgitetaecdh. byte. When CTS#
O
ActLow
Async
UwAhRetTh0erRtehqeuUeAstRTtoisSreenadd:yTthoisrebciteiivnedidcaattae.sWtohtehnethreismboitteisdleovwic,ethe
UitsARinTaicstirveea(dhyigtho)restcaetiev.eLdOaOtaP. _{MAordeeseotpoepraetriaotniohnosldestsththisisssigignnaallinto}
its inactive state.
Non-Autoflow Mode:
1
The RTS# outopfutthseigMnoadl _{ecamnCboenatrsosleRrteegdisbteyrsteott1in.gThbeit[R1T]S(RbTitSi)s}
the complement of the RTS# signal.
Autoflow Mode:
RTS# is automtthhaerteicrsaehcloleyldiva.esIstbeiurstffedederabesyxscetehrteeeddasuwitthosfeplonrwoegncroiarumcgumhitrebydywtehseanre
removed from the buffer to lower the data level
back to the threshold.
U1_RXD
1
I
Async
UreAcReTive1 _{sSheirfitarleIgnipsutetr:.} Serial data input from the device pin to the
December 2007
Order Number: 315038-003US
Intel^® 81348 I/ODParotacsehsesoert
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