81348 Datasheet, PDF (12/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Features
2.2.2
Note:
2.2.3
2.2.4
Internal Busses
The 81348 is built around two internal busses: north internal bus and south internal
bus. The two busses use the same bus protocol. The north internal bus is 128 bits wide
and operates at up to 400 MHz. The north bus connects the two Intel XScale^®
processors, which have direct access to the DDR2 SDRAM and SRAM. The Intel XScale^®
processors also have direct access to the SAS/SATAFibre Channel engine memory-
mapped registers. The north XSI bus is designed to provide the two Intel XScale^®
processors with low-latency access.
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Application DMA Controllers
There are three Application DMA Controllers. The Application DMA Controller is dual-
ported—with one of its ports connected to the south XSI bus and the other port to the
DDR2 SDRAM Memory Controller. This Application DMA Controller allows low-latency,
high-throughput data transfers between PCI bus agents and the DDR2 memory. The
DMA controller also allows data transfer between DDR2 Memory. The DMA Controller
supports chaining and unaligned data transfers. It is programmable through the Intel
XScale^® processor and the host processor.
Isnouardcdeist.ion to simple data transfers, the ADMA performs XOR operations with up to 16
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 81348
local memory. The ATU provides interface for the RAID Controller PCI function. The ATU
supports transactions between PCI address space and the 81348 address space.
Address translation is controlled through programmable registers accessible from both
the PCI interface and the Intel XScale^® processor. Dual access to registers allows
flexibility in mapping the two address spaces. The ATU also supports the following
extended capability configuration headers:
1. _SPo_pw_ece_ir_ficM_aa_tn_ioa_ng,eRmeevnistiohnea1d.1e.r, as defined by PCI Bus Power Management Interface
2. _SM_pe_es_cs_ia_fig_ce_atS_ioig_nn, aRleevdisIinotner2r.u3p.t capability structure, as specified in PCI Local Bus
3. _SPC_pI_e-_cX_ifiC_ca_atp_ia_ob_ni_,liRtieevsisLiiostnI1te.0mb,. as specified in the PCI-X Addendum to the Local Bus
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12
December 2007
Order Number: 315038-003US