81348 Datasheet, PDF (71/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Electrical Specifications—Intel^® 81348
4.3.2 DDR2 SDRAM Interface Signal Timings
Table 24.
DDR2 SDRAM Signal Timings
Symbol
Parameter
Min. Max Units Notes
Tvb1 DQ, CB and DM write output valid time before DQS
0.530
ns 1, 3
Tva1 DQ, CB and DM write output valid time after DQS
0.530
ns 1, 3
Tvb2 DQS write output valid time before M_CK (DQS early)
0.200 ns 1, 3
Tva2 DQS write output valid time after M_CK (DQS late)
0.530 ns 1, 3
Tvb3 _{rMisAin, gBAe,dg}^R_e^A_.^{S#, CAS#, WE# write output valid before M_CK} 4.900
ns 1, 3
Tva3 ^MrisAin, _gBAe,dg^R_e^A_.^{S#, CAS#, WE# write output valid after M_CK} 1.530
ns 1, 3
Tvb4 ^{CUSn#bu,fCfeKrEe,dOmDoTdewrite output valid before M_CK rising edge.} 2.090
ns 1, 3
Tva4 ^{CUSn#bu,fCfeKrEe,dOmDoTdewrite output valid after M_CK rising edge.}
0.590
ns 1, 3
Tvb5
CS#, CKE, ODT write output valid before M_CK rising edge.
Registered mode
1.150
ns 1, 3
Tva5 ^{CReSg#is,tCeKreEd, OmDoTdewrite output valid after M_CK rising edge.}
1.530
ns 1, 3
Tis6
DQ, CB read input setup time before DQS rising or falling
edges.
-0.670
ns 2
Tih6 DQ, CB read input hold time after DQS rising or falling edges. 1.250
ns 2
Tov7 M_CK[2:0] output valid from P_CLKIN or REFCLK
0.460 1.930 ns
N_12..otes: _{SSeeee FFiigguurree 1146,, ““DDDDRR22 SSDDRRAAMM WReraitde TTiimmiinnggss”” oonn ppaaggee 8821.. Timings valid when the DQS delay is}
3. SpreoegFraigmumree1d8f,o“rAtCheTedsetfaLuolatd9f0ordeDgDreRe2 ^{pShDaRsAeMshSifitg.nals”} on page 82.
December 2007
Order Number: 315038-003US
Intel^® 81348 I/ODParotacsehsesoert
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