81348 Datasheet, PDF (32/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Package Information
Table 12.
Power and Ground Signals
Name
Count Type
V_CC1P2PLLS0
1 PWR
V_CC1P2PLLS1
1 PWR
V_CC1P2PLLP
1 PWR
V_CC1P2PLLD
1 PWR
V_CC3P3PLLX
VSSPLLS0
VSSPLLS1
VSSPLLP
VSSPLLD
VSSPLLX
V_CC1P2
V_CC1P2AE
V_CC1P2E
V_CC1P2DS
V_CC1P2AS
V_CC1P2X
V_CCVIO
V_CC1P8
V_CC1P8E
V_CC1P8S
V_CC3P3
V_SS
V_SSE
V_SSAS
V_SSDS
Total
1 PWR
1 GND
1 GND
1 GND
1 GND
1 GND
187 PWR
8 PWR
6 PWR
6 PWR
9 PWR
119 PWR
21 PWR
30 PWR
14 PWR
6 PWR
42 PWR
373 GND
20 GND
20 GND
6 GND
877
Description
VPr_{CoCvPidLeLsSptoowraegret:oBoanllecoofntnweoctePdLLtsotaha1t.2coVntfrilotleSretdorbaogaeridntseurpfapclye..}
VPr_{CoCvPidLeLsSptoowraegret:oBoanllecoofntnweoctePdLLtsotaha1t.2coVntfrilotleSretdorbaogaeridntseurpfapclye..}
VPr_{CoCvPidLeLsPpCoIw-Xe:r} BtoalPl _{LcLontnheacttceodnttoroals1t.h2eVPCfiIlt-eXrelodgbicoaanrdd} sinutpeprlfya.ce.
VPr_{CoCvPidLeLsDpDoRw:erBatoll tchoennPeLcLtethdattocaon1t.r2olVs tfhileteDreDdRb2oSarDdRsAuMppinlyt.erface}
and processor digital logic.
VTpho_{CiwCsePprLinLtoXpt:rhoBevaiPdllLeLtsotphboaewtcecoronntnoteraoctlvseodtlhttaeogIaent3ree.l3gXuVSlacftaioltlree,®}rwedphribcohocaesrsudspospruliapenpsdly.XSI
processor logic.
tVh^Se^S lPoLcLatSiotnoroafgeth:eBV^al_C^l_C^to_1P^b₂^e_PL^c_L^o_Sⁿ₀^{nfeilctteer.d to a board ground plane at}
Vth_{SeS lPoLcLatSiotnoroafgeth:eBV}al_Cl_Cto_1Pb₂e_PLc_Lo_Sn₁nfeilctteer.d to a board ground plane at
V_SS PLL PCI-X: Ball connected to capacitor of the V_CC1P2PLLP filter.
fVil^St^Ser.PLL ^{DDR2 SDRAM: Ball connected to capacitor of VCC1P2PLLD}
V_SS PLL X: Ball connected to capacitor of V_CC3P3PLLX filter.
1T.h2esVePpoinwserp:roBvaildlsetpoobweercotonntehcetepdrotcoeass1o.r2loVgibco.ard power plane.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the PCI Express* analog logic.
1T.h2esVePpoinwserp:roBvaildlsetpoobweercotonntehcetePdCItoExap1re.2ssV*bdoigairtdalploowgiecr. plane.
1T.h2esVe Ppoinwserp:roBvaildlse tpoobweercotonntehcetesdtotroagae1in.2teVrfbaocearddigpiotawl elor _gpilca.ne.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the storage interface analog logic.
1T.h2esVePpoinwserp:roBvaildlsetpoobweercotonntehceteIndtteol _{XaS1c.a2leV®}bporaorcdepssoowres.r plane.
VIO Power: Balls to be connected to a 3.3V board power plane.
These pins provide 3.3 V power to the PCI-X I/Os.
1T.h8esVePpoinwserp:roBvaildlsetpoobweercotnontehceteDdDtRo2aS1D.R8AVMbionaterdrfapcoeweI/rOpsl.ane.
1T.h8esVePpoinwserp:roBvaildlsetpoobweercotonntehcetePdCItoExap1re.8ssV*binotaerrdfapcoewIe/Or _sp.lane.
1T.h8esVePpoinwserp:roBvaildlsetpoobweercotonntehcetesdtotroagae1in.8teVrfbaocearId/Opso.wer plane.
3T.h3esVePpoinwserp:roBvaildlse tpoowbeercotonntheectPeBdIt,omais3c.e3llaVnbeooaursdppinosw,earnpdlaPnCeI.-X
I/Os in Mode 1.
Ground: Balls to be connected to a board ground plane.
PCI Express* Ground: Balls connected to a board ground plane.
Analog Storage Ground: Balls connected to a board ground plane.
Digital Storage Ground: Balls connected to a board ground plane.
DInatteal^®sh8e1et348 ^{I/O Processor}
32
December 2007
Order Number: 315038-003US