81348 Datasheet, PDF (18/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Package Information
Table 3.
Peripheral Bus Interface Signals
Name
Count Type
Description
A[24:0]
D[15:0]
POE#
PWE#
PCE[1:0]#
PB_RSTOUT#
Total
25
O Peripheral Address Bus: carries the address bits for the current
Rst(PB) access. The PBI interface can address up to 32 MBytes.
16
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Peripheral Output Enable: indicates whether bus access is write or
1
RAscttO(LPoBw)
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0 = Read
1 = Write
1
RstO(PB) ^{PocorenrnitporhtoeltortahwleWrwitrerititedeaEtenanaatboblleteh:eoinnaddtihcdaerteepssesretidophstehpreaacpleed.reTivphihciseer.pailndceavnicbeewuhseetdhetor}
ActLow 0 = Write
1 = Read
Peripheral Chip Enable: Specifies which of the two memory address
O ranges are associated with the current bus access. The pin remains
2
Rst(PB)
ActLow
v_Na_oli_td_e:dur_{ΩTinhg5e%sthe,ep1ien/n1st6imreΩubsrteussbiesatcpocureslslefsod.rupprotopeVrCoCp3ePr3atwioitnh. external 8.2K}
1
O Peripheral Bus Reset Out: can be used to reset the peripheral
ActLow device. It has the same timing as the internal bus reset.
46
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18
December 2007
Order Number: 315038-003US