81348 Datasheet, PDF (28/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Package Information
Table 9.
I²C and SM Bus Signals
Name
Count Type
Description
SCL0
1
I/O
OD
I²C 0 Clock provides synchronous operation of the I²C bus.
SDA0
1
IO/DO _{I2C 0 Data is used for data transfer and arbitration of the I2C bus.}
SCL1
1
IO/DO _{I2C 1 Clock provides synchronous operation of the I2C bus.}
SDA1
1
IO/DO _{I2C 1 Data is used for data transfer and arbitration of the I2C bus.}
SCL2
1
IO/DO _{I2C 2 Clock provides synchronous operation of the I2C bus.}
SDA2
1
I/O
OD
I²C 2 Data is used for data transfer and arbitration of the I²C bus.
SMBCLK
1
IO/DO _{SM Bus Clock provides synchronous operation of the SM bus.}
SMBDAT
1
I/O
OD
SM Bus Data is used for data transfer and arbitration of the bus.
Total
8
Note: Opuplel-nupdrraeinsisotuotrpduetsperenqdusiroenatnheexbtuesrnloaaldpiunlgl-.up resistor to pull up the signal to 3.3 V. The value of the
DInatteal^®sh8e1et348 ^{I/O Processor}
28
December 2007
Order Number: 315038-003US