81348 Datasheet, PDF(20/89 Page) Intel Corporation – Two Integrated Intel XScale processors

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81348 Datasheet, PDF (20/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

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IntelÂ® 81348âPackage Information

Table 5.

PCI Bus Signals (Sheet 1 of 3)

Name

Count Type

Description

P_AD[63:32]

I/O

Sync(P)

PdCurIinAgddtrheessd/aDtaatpah:aisseth. e upper 32 bits of the PCI data bus driven

Rst(P)

P_AD[31:0]

I/O

Sync(P)

PCI Address/Data: is the multiplexed PCI address and lower 32

bits of the data bus.

Rst(P)

P_CBE[7]#

I/O PCI Bus Command and Byte Enables: are multiplexed on the

Sync(P) same PCI pins. During the address phase, they define the bus

Rst(P)

ActLow

command. During the data phase, they are used as byte

enables.

P_CBE[6]#

I/O PCI Bus Command and Byte Enables: are multiplexed on the

Sync(P) same PCI pins. During the address phase, they define the bus

Rst(P)

ActLow

ceonmabmleasn.d. During the data phase, they are used as byte

P_CBE[5]#

I/O PCI Bus Command and Byte Enables: are multiplexed on the

Sync(P) same PCI pins. During the address phase, they define the bus

Rst(P)

ActLow

ceonmabmleasn.d. During the data phase, they are used as byte

P_CBE[4]#

I/O PCI Bus Command and Byte Enables: are multiplexed on the

Sync(P) same PCI pins. During the address phase, they define the bus

Rst(P)

ActLow

ceonmabmleasn.d. During the data phase, they are used as byte

P_CBE[3]#

I/O

Sync(P)

PsaCmI BeuPsCCI opminms.aDnudrianngdtBhyetaedEdnraebssleps:haasree,mthueltyipdleexfiende othnethbeus

Rst(P)

ActLow

command. During the data phase, they are used as byte

enables.

P_CBE[2]#

I/O PCI Bus Command and Byte Enables: are multiplexed on the

Sync(P)

Rst(P)

ActLow

sceaonmmabemlePasCn.dI.pDinusr.inDgurtihnegdtahteaapdhdarsees,stphheaysaer,ethuesyeddeafsinbeytthee bus

P_CBE[1]#

I/O PCI Bus Command and Byte Enables: are multiplexed on the

Sync(P) same PCI pins. During the address phase, they define the bus

Rst(P)

ActLow

ceonmabmleasn.d. During the data phase, they are used as byte

P_CBE[0]#

I/O PCI Bus Command and Byte Enables: are multiplexed on the

Sync(P) same PCI pins. During the address phase, they define the bus

Rst(P)

ActLow

ceonmabmleasn.d. During the data phase, they are used as byte

P_PAR64

I/O

Sync(P)

PPC_IABDu[s6U3p:3p2er]

DWORD Parity is even

and P_CBE_#[7:4].

parity

across

Rst(P)

P_REQ64#

I/O

Sync(P)

Rst(P)

ActLow

PttrhCaeIntBsaaurcsgteiRotenaqocuknenstothw6el4eP-dCBgIitebsTurtash.nesWfaehtrteeinnmdthpicteawtteaitsrhgtehttheeisaat6tse4sm-ebrptittioconafpoaaf6b4le-,bit

P_ACK64_#.

P_ACK64#

I/O PCI Bus Acknowledge 64-Bit Transfer indicates that the device

Sync(P)

Rst(P)

ActLow

habciatcsdepasostasaitbnivudest.lhyedetacrogdeetdisitws ialldindgretsostarasntshfeertadragteatuosfinthgethceurfruelnl t64-

DInattealÂ®sh8e1et348 I/O Processor

December 2007

Order Number: 315038-003US

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